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ISL6620ACBZ Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL6620ACBZ Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 10 page 5 FN6494.0 April 25, 2008 LGATE Rise Time (Note 4) t_RL VCC = 5V, 3nF load, 10% to 90% 8 ns UGATE Fall Time (Note 4) t_FU VCC = 5V, 3nF load, 10% to 90% 8 ns LGATE Fall Time (Note 4) t_FL VCC = 5V, 3nF load, 10% to 90% 4 ns UGATE Turn-On Propagation Delay (Note 4) t_PDHU VCC = 5V, 3nF load, adaptive 40 ns LGATE Turn-On Propagation Delay (Note 4) t_PDHL VCC = 5V, 3nF load, adaptive 23 ns UGATE Turn-Off Propagation Delay (Note 4) t_PDLU VCC = 5V, 3nF load 18 ns LGATE Turn-Off Propagation Delay (Note 4) t_PDLL VCC = 5V, 3nF load 25 ns Minimum Lgate on time at Diode emulation t_LG_ON_DM VCC = 5V 230 330 450 ns OUTPUT (Note 4) Upper Drive Source Current I_U_Source VCC = 5V, 3nF load 2 A Upper Drive Source Impedance R_U_SOURCE 20mA source current 1 Ω Upper Drive Sink Current I_U_SINK VCC = 5V, 3nF load 2 A Upper Drive Sink Impedance R_U_SINK 20mA sink current 1 Ω Lower Drive Source Current I_L_SOURCE VCC = 5V, 3nF load 2 A Lower Drive Source Impedance R_L_SOURCE 20mA source current 1 Ω Lower Drive Sink Current I_L_SINK VCC = 5V, 3nF load 4 A Lower Drive Sink Impedance R_L_SINK 20mA sink current 0.4 Ω NOTE: 4. Limits should be considered typical and are not production tested. Electrical Specifications Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Functional Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION SOIC DFN 1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET. 2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap Device” on page 7 for guidance in choosing the capacitor value. - 3, 8 NC No connect. 3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation. See “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output of the controller. 4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver. 5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. 6 7 VCC Connect this pin to 5V bias supply. This pin supplies power to the upper gate and lower gate drive. Place a high quality low ESR ceramic capacitor from this pin to GND. 7 9 EN Enable input pin. Connect this pin high to enable driver and low to disable driver. 8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return path for the upper gate drive. - 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection. ISL6620, ISL6620A |
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