6

FN9159.7

May 1, 2012

Three-State Upper Gate Falling Threshold

VCC = 12V

-

2.60

-

V

Shutdown Holdoff Time

-

245

-

ns

UGATE Rise Time

-

26

-

ns

LGATE Rise Time

-

18

-

ns

UGATE Fall Time

-

18

-

ns

LGATE Fall Time

-

12

-

ns

UGATE Turn-On Propagation Delay (Note 7)

-

10

-

ns

LGATE Turn-On Propagation Delay (Note 7)

-

10

-

ns

UGATE Turn-Off Propagation Delay (Note 7)

-

10

-

ns

LGATE Turn-Off Propagation Delay (Note 7)

-

10

-

ns

LG/UG Three-State Propagation Delay (Note 7)

-

10

-

ns

OUTPUT (Note 7)

Upper Drive Source Current

-

1.25

-

A

Upper Drive Source Impedance

1.25

2.0

3.0

Ω

Upper Drive Sink Current

-

2

-

A

Upper Drive Transition Sink Impedance

-

1.3

2.2

Ω

Upper Drive DC Sink Impedance

0.9

1.65

3.0

Ω

Lower Drive Source Current

-

2

-

A

Lower Drive Source Impedance

0.85

1.25

2.2

Ω

Lower Drive Sink Current

-

3

-

A

Lower Drive Sink Impedance

150mA Sink Current

0.60

0.80

1.35

Ω

NOTES:

7. Limits should be considered typical and are not production tested.

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

(Note 8)

TYP

MAX

(Note 8)

UNITS

Functional Pin Description

PACKAGE PIN #

PIN

SYMBOL

FUNCTION

SOIC

DFN

1

1

UGATE

Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.

2

2

BOOT

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap

Device” on page 8 for guidance in choosing the capacitor value.

-

3, 8

N/C

No Connection.

3

4

PWM

The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, See

“Three-State PWM Input” on page 7 for further details. Connect this pin to the PWM output of the controller.

4

5

GND

Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.

5

6

LGATE

Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.

6

7

VCC

Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.

7

9

PVCC

This pin supplies power to both upper and lower gate drives in ISL6613A; only the lower gate drive in ISL6612A. Its

operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.

8

10

PHASE

Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a

return path for the upper gate drive.

9

11

PAD

Connect this pad to the power ground plane (GND) via thermally enhanced connection.

ISL6612A, ISL6613A