4

FN9210.2

January 17, 2006

FAULT DETECTION

Fault Time Out

50

ms

OT

Over-temperature Threshold

140

°C

PG Pull-down Current

VPG > 0.6V

15

µA

VPG < 0.6V

1.7

mA

LOGIC ENABLE

Logic High Threshold

2.3

V

Logic Low Threshold

0.8

V

Logic Low Bias Current

0.2

2

µA

Logic High Bias Current

12

18

24

µA

Electrical Specifications

-40°C to 85°C, unless otherwise specified. (Continued)

PARAMETER

DESCRIPTION

CONDITION

MIN

TYP

MAX

UNIT

Pin Descriptions

PIN NAME

PIN NUMBER

DESCRIPTION

1

CDLY

A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault

timeout time

2

DELB

3, 4

LX1, LX2

Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected

5

DRVP

Positive LDO base drive; open drain of an internal N channel FET

6

FBP

Positive LDO voltage feedback input pin; regulates to 1.2V nominal

7

DRVL

Logic LDO base drive; open drain of an internal N channel FET

8

FBL

Logic LDO voltage feedback input pin; regulates to 1.2V nominal

9, 17

SGND

Low noise signal ground

10

DRVN

Negative LDO base drive; open drain of an internal P channel FET

11

FBN

Negative LDO voltage feedback input pin; regulates to 0.2V nominal

12, 13

PGND

Power ground, connected to source of internal N channel boost FET

14

VREF

Bandgap voltage bypass, connect a 0.1µF to SGND

15

CINT

operation

16

FBB

Boost regulator voltage feedback input pin; regulates to 1.2V nominal

18

EN

Enable pin, High = Enable; Low or floating = Disable

19

VDD

Positive supply

20

PG

Push-pull gate drive of optional fault protection FET, when chip is disabled or when a fault has been

detected, this is high

EL7586, EL7586A