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TLS715B0 Datasheet(PDF) 6 Page - Infineon Technologies AG |
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TLS715B0 Datasheet(HTML) 6 Page - Infineon Technologies AG |
6 / 20 page TLS715B0 General Product Characteristics Data Sheet 6 Rev. 1.0, 2015-03-12 4.2 Functional Range Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 2 Functional Range Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input Voltage Range for Normal Operation V I V Q,nom + Vdr – 40 V – P_4.2.1 Extended Input Voltage Range V I,ext 4.0 – 40 V – 1) 1) When V I is between VI,ext.min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V. P_4.2.2 Enable Voltage Range V EN 0 – 40 V – P_4.2.3 Output Capacitor’s Requirements for Stability C Q 1– – µF –2) 2) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% P_4.2.4 Output Capacitor’s ESR ESR(C Q)– – 5 Ω –3) 3) Relevant ESR value at f = 10 kHz P_4.2.5 Junction Temperature T i -40 – 150 °C – P_4.2.6 Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Package Version PG-DSO-8 EP Junction to Case1) 1) Not subject to production test, specified by design R thJC – 13 – K/W – P_4.3.1 Junction to Ambient R thJA – 46 – K/W 2s2p board2) 2) Specified R thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_4.3.2 Junction to Ambient R thJA – 153 – K/W 1s0p board, footprint only3) 3) Specified R thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). P_4.3.3 Junction to Ambient R thJA – 71 – K/W 1s0p board, 300 mm2 heatsink area on PCB3) P_4.3.4 Junction to Ambient R thJA – 59 – K/W 1s0p board, 600 mm2 heatsink area on PCB3) P_4.3.5 |
Similar Part No. - TLS715B0_15 |
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Similar Description - TLS715B0_15 |
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