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X9110TV14I Datasheet(PDF) 6 Page - Intersil Corporation |
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X9110TV14I Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 18 page  6 FN8158.3 February 13, 2008 TABLE 4. IDENTIFICATION BYTE FORMAT TABLE 5. INSTRUCTION BYTE FORMAT Device Instructions Identification Byte (ID and A) The first byte sent to the X9110 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9110; this is fixed as 0101[B] (refer to Table 4). The A0 bit in the ID byte is the internal slave address. The physical device address is defined by the state of the A0 input pin. The slave address is externally specified by the user. The X9110 compares the serial data stream with the address input state; a successful compare of the address bit is required for the X9110 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A0 input can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is used to set the device to either read or write mode. Instruction Byte and Register Selection The next byte sent to the X9110 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 5. Five of the seven instructions are four bytes in length. These instructions are: • Read Wiper Counter Register – read the current wiper position of the selected pot • Write Wiper Counter Register – change current wiper position of the selected pot • Read Data Register – read the contents of the selected data register • Write Data Register – write a new value to the selected data register • Read Status – This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. The Read Status Register instruction is the only unique format (see Figure 4). Two instructions require a two-byte sequence to complete (See Figure 2). These instructions transfer data between the host and the X9110; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: • XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register • XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register See Instruction format for more details. ID3 ID2 ID1 ID0 0 0 A0 R/W 01 01 (MSB) (LSB) DEVICE TYPE IDENTIFIER INTERNAL SLAVE ADDRESS READ OR WRITE BIT I2 I1 I0 0 RB RA 0 0 (MSB) (LSB) INSTRUCTION OPCODE REGISTER SELECTION RB RA REGISTER 0 0 1 1 0 1 0 1 DR0 DR1 DR2 DR3 X9110 |
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