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X9221AUP Datasheet(PDF) 5 Page - Intersil Corporation |
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X9221AUP Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 15 page S T A R T 0101 A3 A2 A1 A0 A I3 I2 I1 I0 0 P0 R1 R0 SCL SDA S T O P C K A C K S T A R T 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 0 P0 R1 R0 SCL SDA S T O P 0 0 D5 D4 D3 D2 D1 D0 C K A C K A C K 5 FN8163.2 August 30, 2006 tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH termi- nal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor seg- ment towards the VL/RL terminal. A detailed illustra- tion of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Figure 3. Two-Byte Command Sequence Figure 4. Three-Byte Command Sequence Figure 5. Increment/Decrement Command Sequined e S T A R T 0 1 0 1 A3 A2 A1 A0 I3 I2 I1 I0 0 P0 R1 R0 SCL SDA S T O P X X I N C 1 I N C 2 I N C n D E C 1 D E C n A C K A C K X9221A |
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