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X9241AUPZ Datasheet(PDF) 5 Page - Intersil Corporation

Part # X9241AUPZ
Description  Non-Volatile/Low Power/2-Wire/64 Taps
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X9241AUPZ Datasheet(HTML) 5 Page - Intersil Corporation

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5
FN8164.7
August 17, 2015
of the wiper to this action will be delayed tSTPWV. A transfer
from WCR current wiper position to a Data Register is a write
to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it may
occur globally, wherein the transfer occurs between all four of
the potentiometers and one of their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9241A; either between the host and one of the Data
Registers or directly between the host and the WCR. These
instructions are: Read WCR, read the current wiper position
of the selected pot; Write WCR, change current wiper
position of the selected pot; Read Data Register, read the
contents of the selected nonvolatile register; Write Data
Register, write a new value to the selected Data Register.
The sequence of operations is shown in Figure 4.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9241A has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
VH/RH terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed illustration
of the sequence and timing for this operation is shown in
Figures 5 and 6 respectively.
S
T
A
R
T
0101
A3
A2
A1
A0
A
I3
I2
I1
I0
P1
P0
R1
R0
SCL
SDA
S
T
O
P
C
K
A
C
K
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
I3
I2
I1
I0
P1 P0 R1 R0
SCL
SDA
S
T
O
P
CM DW D5 D4 D3 D2
D1 D0
C
K
A
C
K
A
C
K
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
S
T
A
R
T
0
1
0
1
A3
A2A1A0
I3
I2
I1
I0
P1 P0
R1 R0
SCL
SDA
S
T
O
P
X
X
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
A
C
K
A
C
K
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
X9241A


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