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X9409WV24Z-2.7 Datasheet(PDF) 9 Page - Intersil Corporation |
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X9409WV24Z-2.7 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 19 page X9409 9 FN8192.6 September 3, 2015 Submit Document Feedback The next 4 bits of the slave address are the device address. The physical device address is defined by the state of the A0 through A3 inputs. The X9409 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9409 to respond with an acknowledge. The A0 through A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9409 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9409 is still busy with the write operation no ACK will be returned. If the X9409 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Instruction Structure The next byte sent to the X9409 contains the instruction and register pointer information. The format is shown in Figure 6. The four high order bits define the instruction. The next 2 bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select, which one of the four potentiometers is to be affected by the instruction. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 7. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9409; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Table 1. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9409 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 9 and 10 respectively. FIGURE 5. ACK POLLING SEQUENCE NONVOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING ISSUE START ISSUE SLAVE ADDRESS ACK RETURNED? FURTHER OPERATION? ISSUE INSTRUCTION ISSUE STOP NO YES YES PROCEED ISSUE STOP NO PROCEED FIGURE 6. INSTRUCTION BYTE FORMAT I1 I2 I3 I0 R1 R0 P1 P0 POT SELECT REGISTER SELECT INSTRUCTIONS |
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