ISL78236

6

FN8624.0

April 28, 2014

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Pin Configuration

ISL78236

(24 LD QFN)

TOP VIEW

LX2

VIN2

VIN2

EN2

PG2

FB2

LX1

VIN1

VIN1

VDD

SS

EN1

1

2

3

4

5

6

18

17

16

15

14

13

24

23

22

21

20

19

78

9

10

11

12

25

PAD

Pin Descriptions

PIN

NUMBER

SYMBOL

DESCRIPTION

1, 24

LX2

Switching node connection for Channel 2.

4

EN2

Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown VOUT2 and discharge output

capacitor when driven to low. Do not leave this pin floating.

5

PG2

Active high Power-Good (PG) indicator for Channel 2. After power-up or EN2 High, this output is a 1ms delayed

Power-Good signal for the Channel 2 output voltage.

6

FB2

The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier.

The output voltage is set by an external resistor divider from VOUT2 connected to FB2. The power-good output and

undervoltage lockout protection circuitry uses FB2 to monitor the Channel 1 regulator output voltage.

7

COMP

COMP pin is treated as a No Connect in dual output mode operation, using only the internal compensation. If the SS pin

is tied to a soft-start capacitor, external compensation is automatically used. An additional external network across

COMP and SGND is required to improve the loop compensation of the amplifier in parallel current sharing operation.

Connect an external RC network on COMP pin for parallel mode operation.

8

NC

No connect pin; please tie to GND for thermal relief.

9

FB1

The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier.

The output voltage is set by an external resistor divider from VOUT1 connected to FB1. The power-good output and

undervoltage lockout protection circuitry uses FB1 to monitor the Channel 1 regulator output voltage.

10

SGND

System ground.

11

PG1

Active high Power-Good (PG) indicator for Channel 1. After power-up or EN1 High, this output is a 1ms delayed

power-good signal for the Channel 1 output voltage.

12

SYNC

Connect to logic high or input voltage VIN. Connect to an external function generator for external synchronization.

Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or to SGND).

13

EN1

Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shut down VOUT1 and discharge

output capacitor when driven to low. Do not leave this pin floating.