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ISL267450AIHZ-T7A Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL267450AIHZ-T7A Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 18 page ISL267440, ISL267450A 11 FN7708.2 June 28, 2012 Functional Description The ISL267440, ISL267450A are based on a successive approximation register (SAR) architecture utilizing capacitive charge redistribution digital to analog converters (DACs). Figure 21 shows a simplified representation of the converter. During the acquisition phase (ACQ) the differential input is stored on the sampling capacitors (CS). The comparator is in a balanced state since the switch across its inputs is closed. The signal is fully acquired after tACQ has elapsed, and the switches then transition to the conversion phase (CONV) so the stored voltage may be converted to digital format. The comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). The comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the MSB. The SAR logic then forces the capacitive DACs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. Again, the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. This process repeats until all 12 bits have been resolved. An external clock must be applied to the SCLOCK pin to generate a conversion result. The allowable frequency range for SCLOCK is 10kHz to 18MHz (556SPS to 1MSPS). Serial output data is transmitted on the falling edge of SCLOCK. The receiving device (FPGA, DSP or Microcontroller) may latch the data on the rising edge of SCLOCK to maximize set-up and hold times. A stable, low-noise reference voltage must be applied to the VREF pin to set the full-scale input range and common-mode voltage. See “Voltage Reference Input” on page 12 for more details. ADC Transfer Function The output coding for the ISL267440, ISL267450A is twos complement. The first code transition occurs at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size of the ISL267450A is 2*VREF/4096, while the LSB size of the ISL267440 is 2*VREF/1024. The ideal transfer characteristic of the ISL267440, ISL267450A is shown in Figure 22. Analog Input The ISL267440, ISL267450A feature a fully differential input with a nominal full-scale range equal to twice the applied VREF voltage. Each input swings VREF VP-P, 180° out of phase from one another for a total differential input of 2*VREF (refer to Figure 23). Differential signaling offers several benefits over a single-ended input, such as: • Doubling of the full-scale input range (and therefore the dynamic range) • Improved even order harmonic distortion • Better noise immunity due to common mode rejection Figure 24 shows the relationship between the reference voltage and the full-scale input range for two different values of VREF. FIGURE 21. SAR ADC ARCHITECTURAL BLOCK DIAGRAM VIN + VIN – VREF ACQ CONV ACQ ACQ CONV CONV SAR LOGIC CS CS FIGURE 22. IDEAL TRANSFER CHARACTERISTICS FIGURE 23. DIFFERENTIAL INPUT SIGNALING 1LSB = 2•VREF/4096 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 ANALOG INPUT VIN+ – (VIN–) –VREF + ½LSB +VREF – 1½LSB 0V +VREF – 1LSB ISL267440, ISL267450A VCM VREF P-P VREF P-P VIN + VIN – |
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