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ISL29043IROMZ-EVALZ Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL29043IROMZ-EVALZ Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 16 page ISL29043 5 FN7935.0 February 9, 2012 tHD:STA Hold Time (Repeated) START Condition After this period, the first clock pulse is generated. 600 ns tLOW LOW Period of the SCL Clock Measured at the 30% of VDD crossing. 1300 ns tHIGH HIGH period of the SCL Clock 600 ns tSU:STA Set-up Time for a Repeated START Condition 600 ns tHD:DAT Data Hold Time 30 ns tSU:DAT Data Set-up Time 100 ns tR Rise Time of both SDA and SCL Signals (Note 12) 20 + 0.1xCb ns tF Fall Time of both SDA and SCL Signals (Note 12) 20 + 0.1xCb ns tSU:STO Set-up Time for STOP Condition 600 ns tBUF Bus Free Time Between a STOP and START Condition 1300 ns Cb Capacitive Load for Each Bus Line 400 pF Rpull-up SDA and SCL System Bus Pull-up Resistor Maximum is determined by tR and tF 1k Ω tVD;DAT Data Valid Time 0.9 µs tVD:ACK Data Valid Acknowledge Time 0.9 µs VnL Noise Margin at the Low Level 0.1VDD V VnH Noise Margin at the High Level 0.2VDD V NOTES: 11. All parameters in I2C Electrical Specifications table are guaranteed by design and simulation. 12. Cb is the capacitance of the bus in pF. I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance (Note 11). (Continued) PARAMETER DESCRIPTION CONDITION MIN (Note 7) TYP MAX (Note 7) UNIT FIGURE 3. I2C TIMING DIAGRAM |
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