Datasheet

10

Rev. 1.2, 2014-10-17

TLE4678

General Product Characteristics

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards.

For more information, go to

www.jedec.org.

Parameter

Symbol

Limit Values

Unit

Conditions

Number

Min.

Typ.

Max.

TLE4678GM (PG-DSO-14)

–

27

–

K/W

Pins 3 - 5 and 10 - 12

1) Not subject to production test; specified by design.

4.3.1

Junction – Ambient

–

104

–

K/W

Footprint only 1) 2)

(Chip+Package) was simulated on a 76.2

4.3.2

–

73

–

K/W

heatsink area 1) 2)

4.3.3

–

65

–

K/W

heatsink area 1) 2)

4.3.4

–63

–

K/W

2s2p PCB 1) 3)

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

4.3.5

TLE4678EL (PG-SSOP-14)

Junction to Case

–10

–

K/W

– 1)

4.3.6

Junction to Ambient

–

140

–

K/W

Footprint only 1) 2)

4.3.7

–

63

–

K/W

heatsink area 1) 2)

4.3.8

–

53

–

K/W

heatsink area 1) 2)

4.3.9

–47

–

K/W

2s2p PCB 1) 3)

4.3.10