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HCS301-IP Datasheet(PDF) 11 Page - Microchip Technology |
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HCS301-IP Datasheet(HTML) 11 Page - Microchip Technology |
11 / 20 page © 1996 Microchip Technology Inc. Preliminary DS21143A-page 11 HCS301 6.0 PROGRAMMING THE HCS301 When using the HCS301 in a system, the user will have to program some parameters into the device including the serial number and the secret key before it can be used. The programming cycle allows the user to input all 192 bits in a serial data stream, which are then stored internally in EEPROM. Programming will be initiated by forcing the PWM line high, after the S3 line has been held high for the appropriate length of time line (Table 6-1 and Figure 6-1). After the program mode is entered, a delay must be provided to the device for the automatic bulk write cycle to complete. This will write all locations in the EEPROM to an all zeros pat- tern. The device can then be programmed by clocking in 16 bits at a time, using S3 as the clock line and PWM as the data in line. After each 16-bit word is loaded, a programming delay is required for the internal program cycle to complete. This delay can take up to Twc. At the end of the programming cycle, the device can be veri- fied (Figure 6-2) by reading back the EEPROM. Read- ing is done by clocking the S3 line and reading the data bits on PWM. For security reasons, it is not possible to execute a verify function without first programming the EEPROM. A verify operation can only be done immediately following the program cycle. Note: To ensure that the device does not acci- dentally enter programming mode (result- ing in a bulk erase), PWM should never be pulled high by the circuit connected to it. Special care should be taken when driving PNP RF transistors. FIGURE 6-1: PROGRAMMING WAVEFORMS FIGURE 6-2: VERIFY WAVEFORMS TABLE 6-1: PROGRAMMING/VERIFY TIMING REQUIREMENTS VDD = 5.0V ± 10% 25 ° C ± 5 °C Parameter Symbol Min. Max. Units Program mode setup time TPS 3.5 4.5 ms Hold time 1 TPH1 3.5 — ms Hold time 2 TPH250 — µs Bulk Write time TPBW — 2.2 ms Program delay time TPROG — 2.2 ms Program cycle time TWC —36 ms Clock low time TCLKL 25 — µs Clock high time TCLKH 25 — µs Data setup time TDS 0— µs Data hold time TDH 18 — µs Data out valid time TDV 10 24 µs PWM Enter Program Mode (Data) (Clock) Bit 0 Bit 1 Bit 2 Bit 3 Bit 14 Bit 15 Bit 16 Bit 17 TPH1 TPBW TPS Repeat 12 times for each word TPH2 TCLKH TCLKL TWC TDS S3 Data for Word 0 (KEY_0) Data for Word 1 TDH Note 1: Unused button inputs to be held ground during the entire programming sequence. 2: The VDD pin must be taken to ground after a programming/verify cycle. PWM (Clock) (Data) End of Programming Cycle Begin Verify Cycle Here Bit 1 Bit 2 Bit 3 Bit 15 Bit 14 Bit 16 Bit 17 Bit190 Bit191 TWC Data in Word 0 TDV S3 Bit 0 Bit191 Bit190 Note: If a verify operation is to be done, then it must immediately follow the program cycle. |
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