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TLF80511EJ Datasheet(PDF) 5 Page - Infineon Technologies AG |
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TLF80511EJ Datasheet(HTML) 5 Page - Infineon Technologies AG |
5 / 20 page ![]() Data Sheet 5 Rev. 1.0, 2014-11-17 TLF80511EJ Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-DSO8-EP Figure 2 Pin Configuration 3.2 Pin Definitions and Functions PG-DSO8-EP Pin Symbol Function 1I Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended 2GND Ground 3n.c. Not connected Leave open or connect to GND 4Q Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in the table “Functional Range” on Page 7 5, 6, 7, 8 n.c. Not connected Leave open or connect to GND Pad - Exposed Pad Connect to heatsink area; Connect with GND on PCB n.c. n.c. n.c. I GND n.c. Qn.c. 1 3 2 8 7 6 45 |
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