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TLS810C1EJV33 Datasheet(PDF) 8 Page - Infineon Technologies AG

Part # TLS810C1EJV33
Description  Ultra Low Quiescent Current Linear Voltage Regulator
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLS810C1EJV33 Datasheet(HTML) 8 Page - Infineon Technologies AG

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TLS810C1EJV33
General Product Characteristics
Data Sheet
8
Rev. 1.0, 2015-02-11
4.2
Functional Range
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 2
Functional Range
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
Input Voltage Range
V
I
V
Q,nom
+
V
dr
–42
V
1)
1) Output current is limited internally and depends on the input voltage, see Electrical Characteristics for more details.
P_4.2.1
Extended Input Voltage Range
V
I,ext
2.75
42
V
2)
2) When
V
I is between VI,ext.min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V.
P_4.2.2
Output Capacitor
C
Q
1
µF
3)
3) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.
P_4.2.3
Output Capacitor’s ESR
ESR(
C
Q)–
100
4)
4) Relevant ESR value at
f = 10 kHz.
P_4.2.4
Junction temperature
T
j
-40
150
°C
P_4.2.5
Table 3
Thermal Resistance
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min.
Typ.
Max.
Package Version PG-DSO-8 EP
Junction to Case1)
1) Not subject to production test, specified by design
R
thJC
19
K/W
P_4.3.1
Junction to Ambient1)
R
thJA
51
K/W
2s2p board2)
2) Specified
R
thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
P_4.3.2
Junction to Ambient1)
R
thJA
167
K/W
1s0p board, footprint
only3)
3) Specified
R
thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
P_4.3.3
Junction to Ambient1)
R
thJA
71
K/W
1s0p board, 300 mm2
heatsink area on PCB3)
P_4.3.4
Junction to Ambient1)
R
thJA
60
K/W
1s0p board, 600 mm2
heatsink area on PCB3)
P_4.3.5


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