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MCP2510-ISO Datasheet(PDF) 38 Page - Microchip Technology |
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MCP2510-ISO Datasheet(HTML) 38 Page - Microchip Technology |
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38 / 76 page  MCP2510 DS21291C-page 38 Preliminary 2000 Microchip Technology Inc. FIGURE 5-3: Shortening a Bit Period 5.8 Programming Time Segments Some requirements for programming of the time seg- ments: • Prop Seg + Phase Seg 1 >= Phase Seg 2 • Prop Seg + Phase Seg 1 >= TDELAY • Phase Seg 2 > Sync Jump Width For example, assuming that a 125 kHz CAN baud rate with FOSC = 20 MHz is desired: TOSC = 50 nsec, choose BRP<5:0> = 04h, then TQ = 500nsec. To obtain 125 kHz, the bit time must be 16 TQ. Typically, the sampling of the bit should take place at about 60-70% of the bit time, depending on the system parameters. Also, typically, the TDELAY is 1-2 TQ. Sync Seg = 1 TQ; Prop Seg = 2 TQ; So setting Phase Seg 1 = 7 TQ would place the sample at 10 TQ after the transition. This would leave 6 TQ for Phase Seg 2. Since Phase Seg 2 is 6, by the rules, SJW could be the maximum of 4 TQ. However, normally a large SJW is only necessary when the clock generation of the differ- ent nodes is inaccurate or unstable, such as using ceramic resonators. So an SJW of 1 is typically enough. 5.9 Oscillator Tolerance The bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 kbit/sec, as a rule of thumb. For the full bus speed range of the CAN protocol, a quartz oscillator is required. A maximum node-to-node oscillator variation of 1.7% is allowed. Input Signal Sync Prop Segment Phase Segment 1 Phase Segment 2 ≤ SJW Sample Actual Nominal Bit Length T Q Point Bit Length |
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Similar Description - MCP2510-ISO |
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