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MCP2510-IST Datasheet(PDF) 15 Page - Microchip Technology

Part # MCP2510-IST
Description  Stand-Alone CAN Controller with SPI Interface
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP2510-IST Datasheet(HTML) 15 Page - Microchip Technology

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 2000 Microchip Technology Inc.
Preliminary
DS21291C-page 15
MCP2510
3.0
MESSAGE TRANSMISSION
3.1
Transmit Buffers
The MCP2510 implements three Transmit Buffers. Each
of these buffers occupies 14 bytes of SRAM and are
mapped into the device memory maps. The first byte,
TXBNCTRL, is a control register associated with the mes-
sage buffer. The information in this register determines
the conditions under which the message will be transmit-
ted and indicates the status of the message transmission.
(see Register 3-2). Five bytes are used to hold the stan-
dard and extended identifiers and other message arbitra-
tion information (see Register 3-3 through Register 3-8).
The last eight bytes are for the eight possible data bytes
of the message to be transmitted (see Register 3-8).
For the MCU to have write access to the message buffer,
the TXBNCTRL.TXREQ bit must be clear, indicating that
the message buffer is clear of any pending message to be
transmitted. At a minimum, the TXBNSIDH, TXBNSIDL,
and TXBNDLC registers must be loaded. If data bytes are
present in the message, the TXBNDm registers must also
be loaded. If the message is to use extended identifiers,
the TXBNEIDm registers must also be loaded and the
TXBNSIDL.EXIDE bit set.
Prior to sending the message, the MCU must initialize
the CANINTE.TXINE bit to enable or disable the gener-
ation of an interrupt when the message is sent. The
MCU must also initialize the TXBNCTRL.TXP priority
bits (see Section 3.2).
3.2
Transmit Priority
Transmit priority is a prioritization, within the MCP2510,
of the pending transmittable messages. This is indepen-
dent from, and not necessarily related to, any prioritiza-
tion implicit in the message arbitration scheme built into
the CAN protocol. Prior to sending the SOF, the priority
of all buffers that are queued for transmission is com-
pared. The transmit buffer with the highest priority will be
sent first. For example, if transmit buffer 0 has a higher
priority setting than transmit buffer 1, buffer 0 will be sent
first. If two buffers have the same priority setting, the
buffer with the highest buffer number will be sent first. For
example, if transmit buffer 1 has the same priority setting
as transmit buffer 0, buffer 1 will be sent first. There are
four levels of transmit priority. If TXBNCTRL.TXP<1:0>
for a particular message buffer is set to 11, that buffer has
the highest possible priority. If TXBNCTRL.TXP<1:0> for
a particular message buffer is 00, that buffer has the low-
est possible priority.
3.3
Initiating Transmission
To initiate message transmission the TXBNCTRL.TXREQ
bit must be set for each buffer to be transmitted. This can
be done by writing to the register via the SPI interface or
by setting the TXNRTS pin low for the particular transmit
buffer(s) that are to be transmitted. If transmission is initi-
ated via the SPI interface, the TXREQ bit can be set at the
same time as the TXP priority bits.
When TXBNCTRL.TXREQ is set, the TXBNCTRL.ABTF,
TXBNCTRL.MLOA and TXBNCTRL.TXERR bits will be
cleared.
Setting the TXBNCTRL.TXREQ bit does not initiate a
message transmission, it merely flags a message
buffer as ready for transmission. Transmission will start
when the device detects that the bus is available. The
device will then begin transmission of the highest prior-
ity message that is ready.
When the transmission has completed successfully the
TXBNCTRL.TXREQ bit will be cleared, the CAN-
INTF.TXNIF bit will be set, and an interrupt will be gen-
erated if the CANINTE.TXNIE bit is set.
If
the
message
transmission
fails,
the
TXBNC-
TRL.TXREQ will remain set indicating that the message is
still pending for transmission and one of the following con-
dition flags will be set. If the message started to transmit
but encountered an error condition, the TXBNCTRL.
TXERR and the CANINTF.MERRF bits will be set and an
interrupt will be generated on the INT pin if the CAN-
INTE.MERRE bit is set. If the message lost arbitration the
TXBNCTRL.MLOA bit will be set.
3.4
TXnRTS Pins
The TXNRTS Pins are input pins that can be configured
as request-to-send inputs, which provides a secondary
means of initiating the transmission of a message from
any of the transmit buffers, or as standard digital inputs.
Configuration and control of these pins is accomplished
using the TXRTSCTRL register (see Register 3-2). The
TXRTSCTRL register can only be modified when the
MCP2510 is in configuration mode (see Section 9.0). If
configured to operate as a request to send pin, the pin
is mapped into the respective TXBNCTRL.TXREQ bit
for the transmit buffer. The TXREQ bit is latched by the
falling edge of the TXNRTS pin. The TXNRTS pins are
designed to allow them to be tied directly to the RXNBF
pins to automatically initiate a message transmission
when the RXNBF pin goes low. The TXNRTS pins have
internal pullup resistors of 100K ohms (nominal).
3.5
Aborting Transmission
The MCU can request to abort a message in a specific
message buffer by clearing the associated TXBnC-
TRL.TXREQ bit. Also, all pending messages can be
requested to be aborted by setting the CAN-
CTRL.ABAT bit. If the CANCTRL.ABAT bit is set to
abort all pending messages, the user MUST reset this
bit (typically after the user verifies that all TXREQ bits
have been cleared) to continue trasmit messages. The
CANCTRL.ABTF flag will only be set if the abort was
requested via the CANCTRL.ABAT bit. Aborting a mes-
sage by resetting the TXREQ bit does NOT cause the
ATBF bit to be set.
Only messages that have not already begun to be
transmitted can be aborted. Once a message has
begun transmission, it will not be possible for the user
to reset the TXBnCTRL.TXREQ bit. After transmission


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