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HS1-3182-8 Datasheet(PDF) 1 Page - Intersil Corporation |
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HS1-3182-8 Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 7 page 1 ® FN2963.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-3182 ARINC 429 Bus Interface Line Driver Circuit The HS-3182 is a monolithic dielectric ally isolated bipolar differential line driver designed to meet the specifications of ARINC 429. This device is intended to be used with a companion chip, HS-3282 CMOS ARINC Bus Interface Circuit, which provides the data formatting and processor interface function. All logic inputs are TTL and CMOS compatible. In addition to the DATA (A) and DATA (B) inputs, there are also inputs for CLOCK and SYNC signals which are AND’d with the DATA inputs. This feature enhances system performance and allows the HS-3182 to be used with devices other than the HS-3182. Three power supplies are necessary to operate the HS-3182: +V = +15V ±10%, -V = -15V ±10%, and V1 = 5V ±5%. VREF is used to program the differential output voltage swing such that VOUT (DIFF) = ±2VREF. Typically, VREF = V1 = 5V ±5%, but a separate power supply may be used for VREF which should not exceed 6V. The driver output impedance is 75 Ω ±20% at +25°C. Driver output rise and fall times are independently programmed through the use of two external capacitors connected to the CA and CB inputs. Typical capacitor values are CA = CB = 75pF for high-speed operation (100kBPS), and CA = CB = 300pF for low-speed operation (12kBPS to 14.5kBPS). The outputs are protected against overvoltage and short circuit as shown in the Block Diagram. The HS-3182 is designed to operate over an ambient temperature range of -55°C to +125°C, or -40°C to +85°C. Features • RoHS/Pb-free Available for SBDIP Package (100% Gold Termination Finish) • TTL and CMOS Compatible Inputs • Adjustable Rise and Fall Times via Two External Capacitors • Programmable Output Differential Voltage via VREF Input • Operates at Data Rates Up to 100k Bits/s • Output Short Circuit Proof and Contains Overvoltage Protection • Outputs are Inhibited (0V) If DATA (A) and DATA (B) Inputs are Both in the “Logic One” State • DATA (A) and DATA (B) Signals are “AND’d” with Clock and Sync Signals • Full Military Temperature Range Pinouts HS-3182 (16 LD SBDIP) TOP VIEW HS-3182 (28 LD CLCC) TOP VIEW TABLE 1. TRUTH TABLE SYNC CLK DATA (A) DATA (B) AOUT BOUT COMMENTS XL X X 0V 0V Null LX X X 0V 0V Null HH L L 0V 0V Null HH L H -VREF +VREF Low HH H L +VREF -VREF High HH H H 0V 0V Null 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 VREF GND SYNC DATA (A) CA AOUT GND -V V1 CLK DATA (B) CB BOUT NC +V NC 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 NC DATA (A) NC NC CA NC NC CLK NC DATA (B) CB NC NC NC Data Sheet May 30, 2008 |
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