6

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 2A. MEASUREMENT POINTS

capacitance.

FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3A. MEASUREMENT POINTS

Reconfigure accordingly to test SW3 and SW4.

FIGURE 3B. TEST CIRCUIT

FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY)

Repeat test for all switches.

FIGURE 4. OFF ISOLATION TEST CIRCUIT

Repeat test for all switches.

ON

OFF

ON

Q =

SWITCH

OUTPUT

LOGIC

INPUT

3V

0V

GND

COM

NO OR NC

V+

C

LOGIC

INPUT

IN

C

V-

90%

3V

0V

0V

LOGIC

INPUT

SWITCH

OUTPUT

SWITCH

OUTPUT

90%

0V

90%

90%

LOGIC

INPUT

IN1

COM1

300



35pF

COM2

300



35pF

NO1

NC2

GND

IN2

V+

C

C

V-

C

ANALYZER

SIGNAL

GENERATOR

V+

C

0V OR 2.4V

NO OR NC

COM

IN

GND

C

V-

V+

C

0.8V OR 2.4V

NO OR NC

COM

IN

GND

1mA

C

V-

ISL84521, ISL84522, ISL84523