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X28HC256SI-90 Datasheet(PDF) 8 Page - Intersil Corporation |
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X28HC256SI-90 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 19 page X28HC256 8 FN8108.5 August 27, 2015 Submit Document Feedback Page Write Cycle WE OE LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n + 1 BYTE n + 2 tWP tWPH tBLC tWC CE ADDRESS I/O OE (Note 13) (Note 14, 15) NOTES: 13. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 14. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 15. For each successive write within the page write operation, A7 to A15 should be the same or writes to an unknown address could occur. FIGURE 6. PAGE WRITE CYCLE |
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