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TC850ILW Datasheet(PDF) 10 Page - Microchip Technology |
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TC850ILW Datasheet(HTML) 10 Page - Microchip Technology |
10 / 26 page TC850 DS21479C-page 10 © 2006 Microchip Technology Inc. 4.2 Zero Integrator Phase During the zero integrator phase, the differential input signal is disconnected from the circuit by opening inter- nal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input con- dition. At the same time, a feedback loop is closed around the input buffer, integrator and comparator. The feedback loop ensures the integrator output is near 0V before the signal integrate phase begins. During this phase, a chopper-stabilization technique is used to cancel offset errors in the input buffer, integra- tor and comparator. Error voltages are stored on the CBUFF, CINT and COMP capacitors. The zero integrate phase requires 246 clock cycles. 4.3 Signal Integrate Phase The zero integrator loop is opened and the internal dif- ferential inputs are connected to IN+ and IN-. The differ- ential input signal is integrated for a fixed time period. The TC850 signal integrate period is 256 clock periods, or counts. The crystal oscillator frequency is ÷4 before clocking the internal counters. The integration time period is: EQUATION 4-1: 4.4 Reference Integrate Phase During reference integrate phase, the charge stored on the integrator capacitor is discharged. The time required to discharge the capacitor is proportional to the analog input voltage. The reference integrate phase is divided into three subphases: 1. Fast 2. Slow 3. Overrange de-integrate During fast de-integrate, VIN- is internally connected to analog common and VIN+ is connected across the pre- viously-charged reference capacitor (CREF1). The inte- grator capacitor is rapidly discharged for a maximum of 512 internal clock pulses, yielding 9 bits of resolution. During the slow de-integrate phase, the internal VIN+ node is now connected to the CREF2 capacitor and the residual charge on the integrator capacitor is further discharged a maximum of 64 clock pulses. At this point, the analog input voltage has been converted with 15 bits of resolution. If the analog input is greater than full scale, the TC850 performs up to three overrange de-integrate sub- phases. Each subphase occupies a maximum of 64 clock pulses. The overrange feature permits analog inputs up to 192 LSBs greater than full scale to be correctly converted. This feature permits the user to digitally null up to 192 counts of input offset, while retaining full 15-bit resolution. In addition to 512 counts of fast, 64 counts of slow and 192 counts of overrange de-integrate, the reference integrate phase uses 10 clock pulses to permit internal nodes to settle. Therefore, the reference integrate cycle occupies 778 clock pulses. TINT = 4 x 256 FOSC |
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