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TEA1892TS Datasheet(PDF) 5 Page - NXP Semiconductors |
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TEA1892TS Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 13 page TEA1892TS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 1 — 9 April 2014 5 of 13 NXP Semiconductors TEA1892TS GreenChip synchronous rectifier controller The level of the driver regulation voltage Vreg(drv) can be selected using the SELREG pin. When this SELREG pin is grounded, the typical Vreg(drv) equals 42 mV. When the SELREG pin is left open, the Vreg(drv) level equals 30 mV. Internally, the SELREG pin has a pull-up current source of 10 A. When this pin is short circuited to ground, the pin selects the lowest Vreg(drv). If the pin is left open, the highest Vreg(drv) value is selected. 7.4 Supply management All internal reference voltages are derived from a temperature compensated, on-chip band gap circuit. 7.5 Driver The driver circuit to the external power MOSFET gate has a typical source capability of 400 mA and a typical sink capability of 2.7 A. These capabilities permit fast switch-on and switch-off of the power MOSFET for efficient operation. The source stage is coupled to the timer (see Figure 1). When the timer has finished, the source capability is reduced to a small current (5 mA typical) capable of keeping the driver output voltage at its level. The output voltage of the driver is limited to 10 V (typical). This high output voltage drives all MOSFET brands to the minimum on-state resistance. During start-up conditions (VCC <Vstartup) and undervoltage lockout the driver output voltage is actively pulled low. Fig 3. Synchronous rectification signals |
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