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TLE7273-2 Datasheet(PDF) 8 Page - Infineon Technologies AG |
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TLE7273-2 Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 26 page TLE7273-2 Block Description and Electrical Characteristics Data Sheet 8 Rev. 1.21, 2014-11-19 5 Block Description and Electrical Characteristics 5.1 Description 5.1.1 Power On Reset and Reset Output For an output voltage level of V Q ≥ 1 V, the reset output is held low. When the level of VQ reaches the reset threshold V RT, the signal at RO remains low for the power-up reset delay time tRD. The reset function and timing is illustrated in Figure 4. The reset reaction time t RR avoids wrong triggering caused by short “glitches” on the VQ- line. In case of V Q power down (VQ < VRT for t > tRR) a logic low signal is generated at the pin RO to reset an external microcontroller. The TLE7273-2GV50 and TLE7273-2EV50 feature an integrated pull-up resistor on the reset output while the TLE7273-2GV33 and TLE7273-2GV26 have an open drain output requiring an external pull-up resistor. When connected to a voltage level of 5 V, a recommended value for this external resistor is ≥ 5.6 kΩ. But it’s also possible calculating its value by using the following formula, based on the reset sink current (Example: external pull-up resistor connected to V ext =5 V): R extmin = ΔV / IRO = (Vext - VROmin) / IRO = (5 V - 0.25 V) / 1.0 mA = 4.75 kΩ At low output voltage levels V Q < 1 V the integrated pull-up resistor of the TLE7273-2GV50 is switched off setting the reset output high ohmic. Figure 4 Reset Function and Timing Diagram 5.1.2 Watchdog Operation The watchdog uses a fraction of the charge pump oscillator’s clock signal as timebase. The watchdog timebase can be adjusted using the pins WM1 and WM2 (see Figure 5). The watchdog can be turned off setting WM1 and WM2 to high level. The timing values refer to typ. values with WM1 and WM2 connected to GND (fast watchdog and reset timing). Figure 5 shows the state diagram of the window watchdog (WWD) and the watchdog and reset mode selection. After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time t RD of typ. 16 ms. With the LOW to HIGH transition of the signal at RO the device starts the ignore window time t CW (32 ms). During this window the signal at the WDI pin is ignored. Next the WWD starts the open window which V I AET03526NEW.VSD t V Q t V RT < t RR V RO t V ROL V ROH t RD t RR V RTI t RR |
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