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TPS7B4253-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS7B4253-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 31 page Thermal Pad 1 OUT 20 IN 2 NC 19 EN 3 NC 18 NC 4 NC 17 NC 5 NC 16 NC 6 GND 15 GND 7 NC 14 NC 8 NC 13 NC 9 NC 12 NC 10 FB 11 ADJ Thermal Pad 1 OUT 8 IN 2 NC 7 NC 3 GND 6 GND 4 FB 5 ADJ TPS7B4253-Q1 www.ti.com SLVSCP3A – JANUARY 2015 – REVISED AUGUST 2015 5 Pin Configuration and Functions DDA Package PWP Package 8-Pin SO PowerPAD 20-Pin HTSSOP With Exposed Thermal Pad Top View Top View NC — No internal connection NC — No internal connection Pin Functions PIN TYPE(1) DESCRIPTION NAME SO PowerPAD HTSSOP Connect the reference to this pin. A low signal disables the device and a high signal enables the device. The reference voltage can be connected directly or by a voltage ADJ 5 11 I divider for lower output voltages. To compensate for line influences, connect a capacitor close to the device pins. This pin is the enable pin. The device goes to the STANDBY state when the enable EN — 19 I pin goes lower than the threshold value. This pin is the feedback pin which can connect to the external resistor divider to FB 4 10 I select the output voltage. 3 6 GND G Ground reference 6 15 This pin is the device supply. To compensate for line influences, connect a IN 8 20 I capacitor close to the device pins. 2 3 4 2 5 7 8 NC 9 NC Not connected 12 13 14 7 16 17 18 Block to GND with a capacitor close to the device pins with respect to the OUT 1 1 O capacitance and ESR requirements listed in the Output Capacitor section. Exposed thermal pad — Connect the thermal pad to the GND pin or leave it floating. (1) I = input, O = output, G = ground, NC = no connect Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS7B4253-Q1 |
Similar Part No. - TPS7B4253-Q1_15 |
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Similar Description - TPS7B4253-Q1_15 |
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