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TPS7H1201-HT Datasheet(PDF) 8 Page - Texas Instruments |
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TPS7H1201-HT Datasheet(HTML) 8 Page - Texas Instruments |
8 / 38 page TPS7H1201-HT, TPS7H1101-SP SLVSAS4H – JUNE 2013 – REVISED DECEMBER 2014 www.ti.com 7.4 Thermal Information (1) (2) (3) HKS HKR HKR (HeatSlug_up_no (HeatSlug_down (HeatSlug_down_no THERMAL METRIC(4) UNIT Underfill)(5) Underfill)(6)(7) Underfill) 16 PINS 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance(8) 75.4 30.7 86.6 RθJC(top) Junction-to-case (top) thermal resistance(9) 0.4 N/A N/A RθJB Junction-to-board thermal resistance(10) 4.8 69 59.3 Junction-to-top characterization ψJT 1.1 2.4 5 °C/W parameter(11) Junction-to-board characterization ψJB 53.5 12.3 63.2 parameter(12) Junction-to-case (bottom) thermal RθJC(bot) N/A 0.6 0.6 resistance(13) (1) Do not allow package body temperature to exceed 265°C at any time or permanent damage may result. (2) Maximum power dissipation may be limited by overcurrent protection. (3) Test board conditions: (a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch (b) 2-oz. copper traces located on the top of the PCB (c) 2-oz. copper ground planes on the 2 internal layers and bottom layer (d) 48 (0.010-inch) thermal vias located under the device package (4) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (5) Power rating at a specific ambient temperature TA should be determined with a junction temperature below 220°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 220°C for best performance and long-term reliability. (6) Power rating at a specific ambient temperature TA should be determined with a junction temperature below 135°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 230°C for best performance and long-term reliability. (7) Values listed in the underfill column were derived using properties from a composite, generic silver filled epoxy underfill. They are not product specific. (8) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (9) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (10) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (11) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (12) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7). (13) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS7H1201-HT TPS7H1101-SP |
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