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IRQ to MCU.

Two

packet

loss counters

(ARC_CNT and PLOS_CNT) are incremented

each time a packet is lost. The ARC_CNT

counts the number of retransmissions for the

current transaction.

The PLOS_CNT counts

the total number of retransmissions since the

last channel change. ARC_CNT is reset by

initiating a new transaction.

PLOS_CNT is

reset by writing to the RF_CH register. It is

possible

to

use

the

information

in

the

OBSERVE_TX register to make an overall

assessment of the channel quality.

The PTX device will retransmit if its RX FIFO

is full but received ACK frame has payload.

As an alternative for PTX device to auto

retransmit it is possible

to manually set the

RFM73P-S2 to retransmit a packet a number of

times. This is done by the REUSE_TX_PL

command.

When auto acknowledge is enabled, the PRX

device will automatically check the NO_ACK

field in received packet, and if NO_ACK=0, it

will

automatically

send

an

acknowledge

packet to PTX device. If EN_ACK_PAY is set,

and the acknowledge packet can also include

pending payload in TX FIFO.

6.1

TX/RX FIFO

The data FIFOs are used to store payload that

is to be transmitted (TX FIFO) or payload that

is received and ready to be clocked out (RX

FIFO). The FIFO is accessible in both PTX

mode and PRX mode.

There are three levels 32 bytes FIFO for both

TX and RX, supporting

both acknowledge

mode or no acknowledge mode with up to six

pipes.

•

TX three levels, 32 byte FIFO

•

RX three levels, 32 byte FIFO

Both

FIFOs

have

a

controller

and

are

accessible through the SPI by using dedicated

SPI commands. A TX FIFO in PRX can store

payload for ACK packets to three different

PTX devices. If the TX FIFO contains more

than one payload

to a pipe, payloads are

handled using the first in first out principle.

The TX FIFO in a PRX is blocked if all

pending payloads are addressed to pipes where

the link to the PTX is lost. In this case, the

MCU can flush the TX FIFO by using the

FLUSH_TX command.

The RX FIFO in PRX may contain payload

from up to three different PTX devices.

.

A TX FIFO in PTX can have up to three

payloads stored.

The TX FIFO can be written to by three

commands,

W_TX_PAYLOAD

and

W_TX_PAYLOAD_NO_ACK

in PTX mode

and W_ACK_PAYLOAD in PRX mode. All

three commands give access to the TX_PLD

register.

The RX FIFO can be read by the command

R_RX_PAYLOAD

in both PTX

and PRX

mode. This command gives access to the

RX_PLD register.

The payload in TX FIFO in a PTX is NOT

removed if the MAX_RT IRQ is asserted.

In the FIFO_STATUS register it is possible to

read if the TX and RX FIFO are full or empty.

The TX_REUSE bit is also available in the

FIFO_STATUS register. TX_REUSE is set by

the SPI command REUSE_TX_PL, and is

reset

by

the

SPI

command:

W_TX_PAYLOAD or FLUSH TX.

6.2

Interrupt

In RFM73P-S2 there is an active low interrupt

(IRQ) pin, which is activated when TX_DS

IRQ, RX_DR IRQ or MAX_RT IRQ are set

high by the state machine in the STATUS

register. The IRQ pin resets when MCU writes

'1' to the IRQ source bit in the STATUS

register. The IRQ mask in the CONFIG

RFM73P-S2 V2.0