Fremont Micro Devices

FT25C64A DS

PIN DESCRIPTIONS

accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.

(B) Serial Input (SI)

The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is

latched on the rising edge of the serial clock.

(C)Serial Output (SO)

The SO pin is used to transfer data out of the FT25C64A. During a read cycle, data is shifted out on this pin

after the falling edge of the serial clock.

(D) Serial Clock (SCK)

The SCK is used to synchronize the communication between a master and the FT25C64A. Instructions,

addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the

SO pin is updated after the falling edge of the clock input.

This pin is used in conjunction with the WPEN bit in the status register to prohibit writes to the non-volatile

a status register write sequence will disable writing to the status register. If an internal write cycle has

the WPEN bit is set high.

high impedance state.

MEMORY ORGANIZATION

The FT25C64A devices have 256 pages respectively. Since each page has 32 bytes, random word

addressing to FT25C64A will require 13 bits data word addresses respectively.

© 2013 Fremont Micro Devices Inc.

Confidential Rev 0.80

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