t − TIme − 1 ms/div

1 V/div

(5 V/div)

(10 V/ div)

(500 mV/ div)

(500 mV/ div)

T − Time − 2 ms / div

TPS40190

www.ti.com

SLUS658C – JULY 2005 – REVISED JULY 2012

Pre-Bias Outputs

Some applications require that the converter not sink current during startup if a pre-existing voltage is higher than

the output. Since synchronous buck converters inherently sink current some method of overcoming this

characteristic must be employed. Applications that require this operation are typically power rails for a multi

supply processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn

on until there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage.

This is detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this

controller uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage

is commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current

only during the startup sequence.

If the pre-existing voltage is higher than the intended regulation point for the output of the converter, the

converter starts and sinks current when the soft-start time has completed. A typical pre-biased startup is shown

in Figure 8.

Figure 7. TPS40190 Startup Timing

Figure 8. Prebiased Startup Timing

Typical Applications

Some typical applications.

Copyright © 2005–2012, Texas Instruments Incorporated

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