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TPS40400 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS40400 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 82 page  TPS40400 www.ti.com SLUS930C – APRIL 2011 – REVISED OCTOBER 2015 Electrical Characteristics (continued) Unless otherwise stated, these specifications apply for –40°C ≤ TJ ≤ 125°C, VDD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVLO VDD UVLO turn on threshold(5) Factory default settings (minimum) 2.475 2.75 3.025 VUVLO(on) V 2.25 V ≤ VVDD ≤ 20 V, Accuracy(5) –10% 10% 2.75 V ≤ VIN_ON ≤ 18 V VDD UVLO turnoff threshold(5) Factory default settings (minimum) 2.25 2.5 2.75 VUVLO(off) V 2.25 V < VVDD < 20 V, Accuracy(5) –10% 10% 2.75 V < VIN_OFF < 17.6 V REMOTE VOLTAGE SENSE AMPLIFIER VIOFST Input offset voltage –10 10 mV RGAIN Gain-setting resistor(1) 48 60 72 k Ω VVDD > 6.5 V 0 6 VDIFFO Output voltage at DIFFO pin VVDD = 5 V 0 4.5 V VVDD = 3 V 0 2.5 KDIFF Differential gain of amplifier 0.995 1 1.005 V/V VAGBWP Closed-loop bandwidth(1) 2 MHz IVAOP Output source current VSNS+ = VDIFFO = 5 V, VSNS– = 0 V 1 mA IVAOM Output sink current VSNS+ = 0 V, VSNS– = 4.5 V, VDIFFO = 5 V 1 mA POWERGOOD FB pin voltage upper limit for power good on 648 Factory default settings mV VPGON FB pin voltage lower limit for power good on 552 Accuracy 540 mV < VPGON < 660 mV –5% 5% FB pin voltage upper limit for power good off 660 mV Factory default settings VPGOFF FB pin voltage lower limit for power good off 540 Accuracy 528 mV < VPGOFF < 672 mV –5% 5% RPGD Pulldown resistance of PGD pin VFB = 0, IPGOOD = 5 mA 50 Ω Factory default settings , IPGDLK Leakage current 3 15 μA 550 mV < VFB < 650 mV, VPGOOD = 5 V tPGD Delay filter from FB(1) 5 μs OUTPUT VOLTAGE MARGINING VFB slope during margin voltage transition (6) Factory default settings 250 214 188 V/s MRGSLP Accuracy 3 V < VVDD < 20 V, 600 μs < tSS < 9 ms –15% 15% VFBMH FB pin voltage after margin high command Factory default settings 650 660 670 mV VFBML FB pin voltage after margin low command Factory default settings 532 540 548 mV VFBM(max) Maximum FB pin voltage with margin 742 750 758 mV VFBM(min) Minimum FB pin voltage with margin 445 450 455 mV VFB(inc) Resolution of FB steps with margin 2.34 mV OVERVOLTAGE AND UNDERVOLTAGE DETECTION FB pin overvoltage threshold (OV flag) Factory default settings 638 672 705 VOV mV Accuracy 3 V < VVDD < 20 V, 648 mV < VOV < 690 mV –5% 5% FB pin undervoltage threshold (UV flag) Factory default settings 502 528 554 VUV mV 3 V < VVDD < 20 V, Accuracy –5% 5% 510 mV < VOV < 552 mV PMBus INTERFACE VIH High-level input voltage, CLK, DATA, CNTL 2.1 V VIL Low-level input voltage, CLK, DATA, CNTL 0.8 V High-level input current, CLK, DATA, CNTL –10 10 IIH μA CNTL –12 10 Low-level input current, CLK, DATA, CNTL –10 10 IIL μA CNTL –12 10 (5) Although specifications appear to overlap, hysteresis is assured for UVLO turnon and turnoff thresholds. (6) Specified by design. Not production tested. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS40400 |
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