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TPS51221 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS51221 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 40 page TPS51221 www.ti.com............................................................................................................................................... SLVS786A – NOVEMBER 2007 – REVISED MARCH 2009 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. DRVH1 1 High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0 Ω, SW-node referenced floating driver. Drive O voltage corresponds to VBST to SW voltage. DRVH2 24 SW2 25 I/O High-side MOSFET gate driver returns. SW1 32 Always alive 3.3-V, 10-mA low dropout linear regulator output. Bypass to (signal) GND by more than 1- µF VREG3 22 O ceramic capacitor. Runs from VIN supply or from VREG5 when it is switched over to V5SW input. EN1 4 Channel 1 and Channel 2 SMPS enable pins. When turning on, apply greater than 0.55 V and less than 6 V, I or leave floating. Connect to GND to disable. Adjustable soft-start capacitance to be attached here. EN2 21 PGOOD1 5 Power good window comparator outputs for channel 1 and 2. The applied voltage should be less than 6V O and recommended pull-up resistance value is from 100 k Ω to 1 MΩ. PGOOD2 20 SKIPSEL1 6 Skip Mode Selection pin. GND: Continuous Conduction Mode I VREF2: Auto Skip SKIPSEL2 19 VREG3: OOA Auto Skip, maximum 7 skips (use with < 400 kHz) VREG5: OOA Auto Skip, maximum 15 skips (use with more than 400 kHz) CSP1 7 Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should I/O be used to extract voltage drop across DCR. 0.1 µF is a good value to start design. Refer to current sensing CSP2 18 scheme section for more details. CSN1 8 Current sense comparator inputs (–). (See the current sensing scheme section.) Used as power supply for I the current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge. CSN2 17 VFB1 9 I SMPS feedback inputs. Connect the feedback resistor divider and should refer to (signal) GND. VFB2 16 COMP1 10 Loop compensation pin (error amplifier output). Connect R (and C if required) from this pin to VREF2 for I proper loop compensation with current mode operation. COMP2 15 Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for RF 3 I/O synchronization. IMON1 11 O Current monitor outputs for CH1. Adding RC filter is recommended. VREF2 13 O 2-V reference output. Bypass to (signal) GND by 0.22- µF ceramic capacitor. Over current trip level and discharge mode selection pin. GND: VOCL-ULV, Discharge on TRIP 14 I VREF2: VOCL-ULV, Discharge off VREG3: VOCL-LV, Discharge off VREG5: VOCL-LV, Discharge on VREF2 and VREG5 Linear Regulators Enable Pin. When turning on, apply greater than 1.2 V and less than EN 12 I 6 V. Connect to GND to Disable. VBST1 31 Supply inputs for high-side N-channel FET driver (boot strap terminal). Connect a capacitor (0.1 µF or I greater is recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this VBST2 26 pin is an optional. DRVL1 30 O Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, GND referenced driver. DRVL2 27 VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW voltage V5SW 2 I is higher than 4.8 V, the switchover function is enabled. (Note: when switchover is enabled, VREG5 output voltage is approximately the same as the V5SW input voltage.) 5-V, 100-mA low dropout linear regulator output. Bypass to (power) GND using a 10 µF ceramic capacitor. Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW VREG5 29 O when 4.8V or above is provided. (Note: when switch-over (see V5SW description above) is enabled, VREG5 output voltage is approximately the same as V5SW input voltage.) VIN 23 I Supply Input for 5-V and 3.3-V linear regulator. Typically connected to VBAT. GND 28 — Ground Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS51221 |
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