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TPS63060-EP Datasheet(PDF) 3 Page - Texas Instruments |
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TPS63060-EP Datasheet(HTML) 3 Page - Texas Instruments |
3 / 29 page TPS63060-EP www.ti.com SLVSC92 – DECEMBER 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION(1) TJ PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER –55°C to 125°C SON - DSC TPS63060MDSCTEP SLL V62/14602-01XE (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT MIN MAX Voltage range VIN, VOUT, PS/SYNC, EN, FB –0.3 17 V L1, L2 -0.3 VIN+0.3 V FB, VAUX -0.3 7.5 V Operating virtual junction temperature range, TJ –55 150 °C Storage temperature range Tstg -65 150 °C Human Body Model - (HBM) 3 kV ESD rating(2) Machine Model - (MM) 200 V Charge Device Model - (CDM) 1 kV (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TPS63060-EP THERMAL METRIC(1) DSC UNITS 10 PINS θJA Junction-to-ambient thermal resistance(2) 48.7 θJCtop Junction-to-case (top) thermal resistance(3) 54.8 θJB Junction-to-board thermal resistance(4) 19.8 °C/W ψJT Junction-to-top characterization parameter(5) 1.1 ψJB Junction-to-board characterization parameter(6) 19.6 θJCbot Junction-to-case (bottom) thermal resistance(7) 4.2 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS63060-EP |
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