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NCP458RFCCT2G Datasheet(PDF) 10 Page - ON Semiconductor

Part # NCP458RFCCT2G
Description  4 A Single Load Switch for Low Voltage Rail
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP458RFCCT2G Datasheet(HTML) 10 Page - ON Semiconductor

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NCP458R, NCP459
http://onsemi.com
10
FUNCTIONAL DESCRIPTION
Overview
The NCP458R and NCP459 are high side N channel
MOSFET power distribution switch designed to isolate ICs
connected on the battery or DCDC supplies in order to save
energy. The part can be used with a wide range of supply
from 0.75 V to 5.5 V.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing NMOS switch off.
The IN/OUT path is activated with a minimum of VBIAS
min, Vin min and EN forced to high level.
Auto Discharge (Optional − NCP459)
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path ( Pull down NMOS) stays activated as
long as EN pin is set at low level.
In order to limit the current across the internal discharge
Nmosfet, the typical value is set at RDIS value.
Vbias Rail
The core of the IC is supplied thanks to Vbias supply rail
(common +5 V, 3.3 V, 1.8 V, 1.2 V). Indeed, no current
consumption is used on IN pin, allowing to improve power
saving of the rail that must be isolated by the power switch.
If Vbias rail is not available or used, Vbias pin and Vin pin
can be connected together as close as possible the DUT. A
minimum of 1.2 V is necessary to control the IC.
Output rise time − Gate control
The NMOS is control with internal charge pump and
driver. A minimum gate slew rate is internally set to avoid
huge inrush current when EN is set from low to high. The
default gate slew rate depends on Vin level. The higher Vin
level, the longer rise time.
In addition, an external capacitor can be connected
between Gate pin and GND in order to slow down the gate
rising. See electrical table for more details.
Cin and Cout Capacitors
100 nF external capacitors must be connected as close as
possible the DUT for noise immunity and better stability. In
case of input hot plug (input voltage connected with fast
slew rate − few
ms − it’s strongly recommended to avoid big
capacitor connected on the input. That allows to avoid input
over voltage transients.
Reverse Blocking Control (Optional NCP458R)
A reverse blocking control circuitry is embedded to
eliminate leakages from OUT to IN in case of Vout > Vin.
A comparator measures the dropout voltage on the switch
between OUT and IN and turn off the NMOS if this voltage
exceeds specified reverse voltage.


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