UDG−95111

39 W

10 W

5

6

50-W

External

Clock

UDG−95113

Master

Slave

4

5

6

5

6

39 pF

120 W

4.7 k

22 W

UDG−95112

UC2825A-EP

www.ti.com

SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010

Synchronization

The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the

free-running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The

pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge

of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that CLK/LEB no longer

accepts an incoming synchronizing signal.

Figure 9. General Oscillator Synchronization

Figure 10. Two-Unit Interface

Figure 11. Operational Waveforms

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