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ADP3207JCPZ-RL Datasheet(PDF) 1 Page - ON Semiconductor |
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ADP3207JCPZ-RL Datasheet(HTML) 1 Page - ON Semiconductor |
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1 / 29 page  7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller ADP3207 ©2008 SCILLC. All rights reserved. Publication Order Number: February 2008 – Rev. 1 ADP3207/D FEATURES 1-, 2-, or 3-phase operation at up to 750 kHz per phase ±8 mV worst-case differential sensing error over temperature Interleaved PWM outputs for driving external high power MOSFET drivers Automatic power-saving modes maximize efficiency during light load and deeper sleep operation Soft transient control reduces inrush current and audio noise Active current balancing between output phases Independent current limit and load line setting inputs for additional design flexibility Built-in power-good masking supports VID on-the-fly 7-bit digitally programmable 0.3 V to 1.5 V output Overload and short-circuit protection with programmable latch-off delay Built-in clock enable output delays CPU clock until CPU supply voltage stabilizes APPLICATIONS Notebook power supplies for next generation Intel® processors GENERAL DESCRIPTION The ADP32071 is a high efficiency, multiphase, synchronous, buck-switching regulator controller optimized for converting notebook battery voltage into the core supply voltage required by high performance Intel processors. The part uses an internal 7-bit DAC to read voltage identification (VID) code directly from the processor that sets the output voltage. The phase relationship of the output signals can be programmed to provide 1-, 2-, or 3-phase operation, allowing for the construction of up to three interleaved buck-switching stages. The ADP3207 uses a multimode architecture to drive the logic- level PWM outputs at a programmable switching frequency that can be optimized depending on the output current requirement. The part switches between multiphase and single-phase operation to maximize its effectiveness under all load conditions. In addition, the ADP3207 includes a programmable slope function to adjust the output voltage as a function of the load current. As a result, it is always best positioned for a system transient. 1 Patent 6,683,441. FUNCTIONAL BLOCK DIAGRAM RT RRPM RAMPADJ VRPM VCC DELAY UVLO SHUTDOWN AND BIAS THERMAL THROTTLING CONTROL OSCILLATOR GND ADP3207 EN PWRGD ILIMIT PGDELAY CLKEN VRTT PWM2 FB DPRSLP STSET SS PWM3 SW1 CSSUM CSCOMP LLSET SW2 SW3 CSREF PWM1 COMP VID DAC CURRENT LIMIT CIRCUIT CROWBAR CURRENT LIMIT SOFT START/ BOOT/ DEEPER SLEEP CONTROL DAC + 200mV DAC – 300mV CSREF 1.7V CSREF 12 13 14 15 23 22 21 19 18 17 33 32 10 9 28 8 27 31 20 1 30 29 3 2 11 4 7 TTSENSE 25 24 1/2/3 – PHASE DRIVER LOGIC SET RESET RESET RESET EN 26 CMP CMP CMP 16 + – 6 5 34 35 36 37 38 39 40 SOFT START + – + – + – + – CURRENT BALANCING CIRCUIT PRECISION REFERENCE DPRSTP PSI OD DCM Figure 1. The chip also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power- good output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3207 is specified over the extended commercial temperature range of 0°C to 100°C and is available in a 40-lead LFCSP package. |
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