REV. 0

ADP3164

–11–

The required equivalent series resistance (ESR) and capacitance

drive the selection of the type and quantity of the output capaci-

tors. The ESR must be less than or equal to the specified output

be large enough that the voltage across the capacitors, which is

the sum of the resistive and capacitive voltage deviations, does

not deviate beyond the initial resistive step while the inductor

current ramps up or down to the value corresponding to the

new load current.

One can, for example, use thirteen SP-Type OS-CON capaci-

tors from Sanyo, with 820 F capacitance, a 4 V voltage rating,

and 12 m

ESR. The ten capacitors have a maximum total ESR

of 0.92 m

when connected in parallel.

As long as the capacitance of the output capacitor bank is above

a critical value and the regulating loop is compensated with

Analog Devices’ proprietary compensation technique (ADOPT),

the actual capacitance value has no influence on the peak-to-

peak deviation of the output voltage to a full step change in the

load current. The critical capacitance can be calculated as follows:

C

I

RV

L

n

A

mV

nH

mF

OUT CRIT

O

OUT

OUT

()

..

.

80

0 95

1 475

600

4

856

(13)

The critical capacitance limit for this circuit is 8.56 mF, while

the actual capacitance of the thirteen OS-CON capacitors is

13

820 F = 10.66 mF. In this case, the capacitance is safely

above the critical value.

Multilayer ceramic capacitors are also required for high-frequency

decoupling of the processor. The exact number of these MLC

capacitors is a function of the board layout space and parasitics.

Typical designs use twenty to thirty 10 F MLC capacitors

located as close to the processor power pins as is practical.

Feedback Loop Compensation Design for ADOPT

Optimized compensation of the ADP3164 allows the best pos-

sible containment of the peak-to-peak output voltage deviation.

Any practical switching power converter is inherently limited by

the inductor in its output current slew rate to a value much less

than the slew rate of the load. Therefore, any sudden change of

load current will initially flow through the output capacitors,

and assuming that the capacitance of the output capacitor is

larger than the critical value defined by Equation 13, this will

produce a peak output voltage deviation equal to the ESR of the

output capacitor times the load current change.

The optimal implementation of voltage positioning, ADOPT,

will create an output impedance of the power converter that is

entirely resistive over the widest possible frequency range, includ-

ing dc, and equal to the maximum acceptable ESR of the output

capacitor array. With the resistive output impedance, the output

voltage will droop in proportion with the load current at any load

current slew rate; this ensures the optimal positioning and allows

the minimization of the output capacitor bank.

With an ideal current-mode-controlled converter, where the

average inductor current would respond without delay to the

command signal, the resistive output impedance could be

achieved by having a single-pole roll-off of the voltage gain of

the voltage-error amplifier. The pole frequency must coincide

with the ESR zero of the output capacitor bank. The ADP3164

uses constant frequency current-mode control, which is known

to have a nonideal, frequency-dependent command signal to

inductor current transfer function. The frequency dependence

manifests in the form of a pair of complex conjugate poles at

one-half of the switching frequency. A purely resistive output

impedance could be achieved by canceling the complex conjugate

poles with zeros at the same complex frequencies and adding a

third pole equal to the ESR zero of the output capacitor. Such

compensating network would be quite complicated. Fortunately, i

practice it is sufficient to cancel the pair of complex conjugate

poles with a single real zero placed at one-half of the switching

frequency. Although the end result is not a perfectly resistive

output impedance, the remaining frequency dependence causes

only a small percentage of deviation from the ideal resistive

response. The single-pole and single-zero compensation can easily

mined; the capacitance and resistance of the series RC network

are calculated as follows:

C

CR

R

n

fR

C

mF

m

k

kHz

k

nF

OC

OUT

OUT

T

OSC

T

OC

10 7

0 92

748

4

800

7 48

11

..

..

.

(14

zero-setting resistor in series with the compensating capacitor is

R

n

f

C

kHz

nF

k

Z

OSC

OC

4

800

1

159

.

(15

The nearest standard 5% resistor value is 1.5 k . Note that this

Power MOSFETs

In this example, eight N-channel power MOSFETs must be used;

four as the main (control) switches, and the remaining four as

the synchronous rectifier switches. The main selection parameters

minimum gate drive voltage (the supply voltage to the ADP3414)

dictates whether standard threshold or logic-level threshold

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