LC87F2R04A

No.A1622-4/25

High-speed Multiplication/Division Instructions

• 16 bits × 8 bits

(5 tCYC execution time)

• 24 bits × 16 bits

(12 tCYC execution time)

• 16 bits ÷ 8 bits

(8 tCYC execution time)

• 24 bits ÷ 16 bits

(12 tCYC execution time)

Oscillation Circuits

• Internal oscillation circuits

Medium-speed RC oscillation circuit:

For system clock (1MHz)

Multifrequency RC oscillation circuit:

For system clock (8MHz)

• External oscillation circuits

Hi-speed CF oscillation circuit:

For system clock, with internal Rf

System Clock Divider Function

• Can run on low current.

• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and

76.8

μs (at a main clock rate of 10MHz).

Internal reset function

• Power-on reset (POR) function

1) POR reset is generated only at power-on time.

2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and

4.35V) through option configuration.

• Low-voltage detection reset (LVD) function

1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls

below a certain level.

2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,

2.81V, 3.79V, 4.28V).

Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.

1) Oscillation is not halted automatically.

2) There are three ways of resetting the HALT mode.

(1) Setting the reset pin to the low level

(2) System resetting by watchdog timer or low-voltage detection

(3) Occurrence of an interrupt

• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.

1) The CF, RC and crystal oscillators automatically stop operation.

2) There are four ways of resetting the HOLD mode.

(1) Setting the reset pin to the lower level.

(2) System resetting by watchdog timer or low-voltage detection

(3) Having an interrupt source established at either INT0, INT1, INT2, INT4

* INT0 and INT1 HOLD mode reset is available only when level detection is set.

(4) Having an interrupt source established at port 0.

On-chip Debugger

• Supports software debugging with the IC mounted on the target board.

• Software break point setting for debugger.

• Stepwise execution on debugger.

• Real time RAM data monitoring function on debugger.

All the RAM data map can be monitored on screen when the program is running.

(The RAM & SFR data can be changed by screen patch when the program is running)

• Two channels of on-chip debugger pins are available to be compatible with small pin count devices.

DBGP0 (P0), DBGP1 (P1)

Data Security Function (flash versions only)

• Protects the program data stored in flash memory from unauthorized read or copy.

Note: This data security function does not necessarily provide absolute data security.