LC87F7NP6A

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4

 Interrupt Source Flags

31 sources, 10 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests

of the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest

level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest

vector address takes precedence.

No.

Vector Address

Level

Interrupt Source

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/INT4/remote control receiver1

4

0001BH

H or L

INT3/base timer/INT5/ remote control receiver2

5

00023H

H or L

T0H/INT6

6

0002BH

H or L

T1L/T1H/INT7

7

00033H

H or L

SIO0/UART1 receive/ UART2 receive/T8L/T8H

8

0003BH

H or L

SIO1/UART1 transmit/ UART2 transmit

9

00043H

H or L

ADC/MIC/T6/T7/PWM4/PWM5

10

0004BH

H or L

Port 0/T4/T5

Priority levels X > H > L

 Of interrupts of the same level, the one with the smallest vector address takes precedence.

 IFLG (List of interrupt source flag function)

1) Shows a list of interrupt source flags that caused a branching to a particular vector address.

Subroutine Stack Levels

2048 levels maximum (The stack is allocated in RAM.)

High-speed Multiplication/Division Instructions

16 bits  8 bits

(5 tCYC execution time)

24 bits  16 bits

(12 tCYC execution time)

16 bits  8 bits

(8 tCYC execution time)

24 bits  16 bits

(12 tCYC execution time)

Oscillation Circuits

RC oscillation circuit (internal): For system clock

CF oscillation circuit: For system clock, with internal Rf and external Rd

Crystal oscillation circuit: For low-speed system clock, with internal Rf and external Rd

Multifrequency RC oscillation circuit (internal): For system clock

1) Adjustable in ±4

 (typ) increments from the selected center frequency.

2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference.

System Clock Divider Function

Can run on low current.

The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and

76.8

s (at a main clock rate of 10MHz).