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PCA9654EA Datasheet(PDF) 2 Page - ON Semiconductor |
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PCA9654EA Datasheet(HTML) 2 Page - ON Semiconductor |
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2 / 22 page  PCA9654E, PCA9654EA www.onsemi.com 2 BLOCK DIAGRAM Remark: All I/Os are set to inputs at reset. Figure 1. Block Diagram Figure 2. Simplified Schematic of I/Os At power−on reset, all registers return to default values. VDD I/O pin output port register data configuration register DQ CK Q data from shift register write configuration pulse output port register DQ CK write pulse polarity inversion register DQ CK data from shift register write polarity pulse input port register DQ CK read pulse input port register data polarity inversion register data FF data from shift register FF FF FF Q1 Q2 VSS to INT 100 k W |
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