VS-FA72SA50LC

www.vishay.com

Vishay Semiconductors

Revision: 13-Aug-13

6

Document Number: 94782

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Fig. 16 - Maximum Safe Operating Area

Fig. 17a - Switching Time Test Circuit

Fig. 17b - Switching Time Waveforms

Fig. 18a - Unclamped Inductive Test Circuit

Fig. 18b - Unclamped Inductive Waveforms

Fig. 19a - Basic Gate Charge Waveform

Fig. 19b - Gate Charge Test Circuit

1

10

100

1000

1

10

100

1000

10 000

OPERATION IN THIS AREA LIMITED

BY R

DS(on)

Single Pulse

T

T

= 150 C

= 25 C

°

°

J

C

V

- Drain-to-Source Voltage (V)

DS

10 μs

100 μs

1 ms

10 ms

Pulse width

≤ 1 µs

Duty factor

≤ 0.1 %

D.U.T.

10 V

+

-

V

DS

R

D

V

DD

R

G

V

GS

90%

0%

GS

0.01

W

D.U.T

L

+

-

Driver

A

15 V

20 V

R

G

V

DS

I

AS

t

p

V

DD

tp

Charge

10V

D.U.T.

V

DS

I

D

I

G

3 mA

V

GS

.3 µF

50 K

W

.2 µF

12 V

Current regulator

Same type as D.U.T.

Current sampling resistors

+

-