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NCP81105 Datasheet(PDF) 4 Page - ON Semiconductor

Part # NCP81105
Description  DrMOS Supporting 1/2/3 Phase Power Controller
Download  36 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP81105 Datasheet(HTML) 4 Page - ON Semiconductor

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NCP81105, NCP81105H
http://onsemi.com
4
PIN LIST AND DESCRIPTION
Pin
No.
Symbol
Description
1
EN
Logic input. Logic high enables the NCP81105 and logic low disables it.
2
VCC
Power for the internal control circuits. A decoupling capacitor must be connected from this pin to ground.
3
VR_HOT#
Open drain (logic level) output for over−temperature reporting. Low indicates high temp.
4
SDIO
Bidirectional Serial VID data interface.
5
ALERT#
Open drain Serial VID ALERT# output.
6
SCLK
Serial VID clock input.
7
ROSC
This pin outputs a constant current. A resistance from this pin to ground programs the switching fre-
quency.
8
VR_RDY
Open drain output. High indicates that the NCP81105 is regulating the output.
9
TSENSE
Temperature sense input.
10
OD#
Phase Disabling Output, tied to the Enable, SMOD or ZCD_EN# pin of phases 2 and 3 DrMOS. Except
in PS0 mode, this output pulls low to disable the DrMOS if connected to an enable input. If connected to
a DrMOS SMOD or ZCD_EN# input, both HS & LS FETs are held off since PWM2 & PWM3 are also low.
Actively pulls high in PS0 mode.
11
SMOD
Phase 1 Zero Cross Detection (ZCD) disable output. In PS2 & PS3, SMOD pulls LOW when phase 1
inductor current is negative to perform (or allow the DrMOS ZCD function to perform) diode emulation,
and pulls HIGH when phase 1 inductor current is positive. In PS0 & PS1, SMOD stays high to force the
phase 1 DrMOS into Continuous Conduction.
12
PWM2
PWM output to Phase 2 DrMOS
13
PWM3
PWM output to Phase 3 DrMOS
14
PWM1
PWM output to Phase 1 DrMOS
15
DRVON
Enable output for DrMOS
16
IMAX
During startup, a resistor from this pin to ground programs ICC_MAX.
17
INT_SEL
During startup, a resistor from this pin to ground programs the low frequency compensator pole of the
NCP81105 voltage control feedback loop.
18
CSP1
Positive input to phase 1 current sense amplifier for balancing phase currents
19
CSN1
Negative input to phase 1 current sense amplifier
20
CSP3
Positive input to phase 3 current sense amplifier for balancing phase currents
21
CSN3
Negative input to phase 3 current sense amplifier
22
CSP2
Positive input to phase 2 current sense amplifier for balancing phase currents
23
CSN2
Negative input to phase 2 current balance sense amplifier
24
CSREF
Non−inverting input for the total output current sense amplifier. Also, the absolute OVP input.
25
CSSUM
Inverting input of total output current sense amplifier.
26
CSCOMP
Output of total output current sense amplifier.
27
ILIM
Input to program the over−current shutdown threshold.
28
IOUT
Total current monitor output. A resistor from this pin to ground calibrates SVID output current reporting.
29
VRMP
VDC applied to this pin provides feed−forward compensation for the pulsewidth modulator. The current
into this pin controls the slope of PWM ramp. A low voltage on this pin will inhibit NCP81105 startup.
30
VBOOT
During startup, a resistor from this pin to ground programs the BOOT voltage
31
DGAIN
During startup, a resistor from this pin to ground programs the scaling of the output Droop with respect to
the total output current signal produced between CSCOMP and CSREF.
32
COMP
Output of the error amplifier.
33
FB
Error amplifier voltage feedback input.
34
DIFFOUT
Output of the differential remote sense amplifier.
35
VSN
Inverting input to the differential remote sense amplifier (VSS sense).
36
VSP
Non−inverting input to the differential remote sense amplifier (VCC sense).
37
GND
Power supply return (QFN Flag)


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