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SM5170 Datasheet(PDF) 7 Page - Nippon Precision Circuits Inc

Part # SM5170
Description  PLL Synthesizer IC
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Manufacturer  NPC [Nippon Precision Circuits Inc]
Direct Link  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5170 Datasheet(HTML) 7 Page - Nippon Precision Circuits Inc

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SM5170AV
NIPPON PRECISION CIRCUITS—7
Reference Frequency Divider (R-counter) Structure
The reference frequency divider generates a compar-
ator frequency signal (FR), which is input to the
phase comparator, by dividing the reference oscilla-
tor frequency input either from an external signal on
XIN or from a crystal oscillator connected between
XIN and XOUT.
The reference frequency divider is comprised of a
fixed divide-by-4 prescaler and a 16-bit reference
counter.
Reference counter frequency data and LD setting
The reference counter which determines the refer-
ence frequency divider ratio is set by bits 1 to 16.
The lock detect signal output is set by bit 20.
Reference frequency divider example
If the VCO output is (fVCO), the crystal oscillator
frequency is 14.4 MHz and the channel bandwidth
(fCH: comparator frequency (fR)) is 25 kHz, then the
reference frequency divider ratio R is given by:
Therefore, the reference counter count is 144
(0000000010010000)2 .
LD output
The output on LD is set by bit 20.
Bits 15 to 19, bits 21 to 22
Bits 15 to 19 have no meaning, and should be set to
0. Bits 21 and 22 are factory test bits and should also
be set to 0.
Frequency settings
Prescaler
A (= 4)
Reference counter
B
Reference frequency divider ratio
R = A
× B = 4 × B
Counter set ranges
Prescaler
A = 4
Reference counter
B = 5 to 65535
Reference frequency divider ratio range
R = 20 to 262140
Figure 5. Reference counter data and LD output setting format
Reference Counter (16bit : 5 to 65535)
12
345
678
9
10
11
12
13
14
15
16
17
MSB
18
19
20
21
22
23
LSB
22
222
222
22
2222
15
14
13
12
11
10
98
76
5432
22
10
Control bits
Not used (set to 000)
24
LDpin Set bit
Test bits (set to 00)
R
Xtal
f
CH
-----------
Xtal
f
R
-----------
14.4
0.025
-------------
576
4
144
×
===
=
=
Bit 20
LD output
1
N o r mal unlock signal output (normal operation)
0
Unlock signal output OFF, LOW -level output


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