NCP5162

http://onsemi.com

11

Figure 15. NCP5162 OVP Response to an

Input−to−Output Short Circuit by Pulling the Input

Voltage to Ground

M 5.00 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)

External Power Good Circuit

An optional Power Good signal can be generated through

the use of four additional external components (see Figure

16). The threshold voltage of the Power Good signal can be

adjusted per the following equation:

VPower Good +

(R1 ) R2)

0.65 V

R2

This circuit provides an open collector output that drives

the Power Good output to ground for regulator voltages less

Figure 16. Implementing Power Good

with the NCP5162

5.0 V

Power Good

10 k

PN3904

6.2 k

R1

R2

PN3904

10 k

R3

NCP5162

Figure 17. NCP5162 During Power Up. Power

Good Signal is Activated when Output

Voltage Reaches 1.70 V

M 2.50 ms

Trace 4− 5.0 V Input (2.0 V/div.)

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 2− Power Good Signal (2.0 V/div.)

Slope Compensation

the ESR of the output capacitors, that is proportional to the

ripple current through the inductor. To maintain regulation,

PWM comparator, and terminates the switch on−time.

The stringent load transient requirements of modern

microprocessors require the output capacitors to have very

low ESR. The resulting shallow slope presented to the PWM

comparator, due to the very low ESR, can lead to pulse width

jitter and variation caused by both random or synchronous

noise.

Adding slope compensation to the control loop, avoids

erratic operation of the PWM circuit, particularly at lower

duty cycles and higher frequencies, where there is not

enough ramp signal, and provides a more stable switchpoint.