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ACE9050 Datasheet(PDF) 11 Page - Mitel Networks Corporation |
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ACE9050 Datasheet(HTML) 11 Page - Mitel Networks Corporation |
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11 / 52 page  ACE9050 11 ACEBus Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 1 85°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V SynthBus (Note: The SynthBus is not required when the ACE9050 is used as part of the ACE Chipset) tD17VCLH SYNTHCLK SYNTHDATA DTFG LATCH D1-7 D1-6 D3-1 D3-0 tCLH tCLL tCLHLAH tLAH tDAVCLH tCLHDAI Fig.11 SynthBus timing diagram SynthBus Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V 491 488 491 491 491 0·099 0 14 14 Characteristic Value Typ. Max. Min. Programmable width 496 496 496 Conditions Units Symbol TRANSMIT Clock high to Data bus driven Data set-up time Data hold time Clock high to Latch high Latch width 0 and 1 Latch width 3 Clock low Clock high Clock high to data line tristate RECEIVE Data set-up time Data hold time ns ns ns ns ns ms ns ns ns ns ns 12·59 5 tCLHDA tDAVCLH tCLHDAI tCLHLAH tPW01 tPW3 tCLL tCLH tCLHDAZ tDAVCLL tCLLDAI Table 6 ACEBus Read and Write timings >0 Characteristic Value Typ. Max. Min. 3·9 4·0 4·97 952 3·99 3·93 Conditions Units Symbol First data bit set-up time Data bit set-up time (except first) Data hold time Clock high to latch high Latch width Clock low Clock high µs µs µs µs ns µs µs 7·84 tD17VCLH tDAVCLH tCLHDAI tCLHLAH tLAH tCLL tCLH Table 7 SynthBus timing |
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