© Semiconductor Components Industries, LLC, 2006

June, 2006 − Rev. 3

1

Publication Order Number:

74ALVCH16240/D

74ALVCH16240

Low−Voltage 16−Bit Buffer

with Bus Hold 1.8/2.5/3.3 V

(3−State, Inverting)

The 74ALVCH16240 is an advanced performance, inverting 16−bit

buffer. It is designed for very high−speed, very low−power operation

in 1.8 V, 2.5 V or 3.3 V systems.

The 74ALVCH16240 is nibble controlled with each nibble

functioning identically, but independently. The control pins may be

tied together to obtain full 16−bit operation. The 3−state outputs are

controlled by an Output Enable (OEn) input for each nibble. When

OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are

in the high impedance state. The data inputs include active bus−hold

circuitry, eliminating the need for external pull−up resistors to hold

unused or floating inputs at a valid logic state.

3.7 ns Max for 2.3 to 2.7 V

6.0 ns Max for 1.65 to 1.95 V

±12 mA Drive at 2.3 V

±4 mA Drive at 1.65 V

Valid Logic State

Substantially Reduces System Power Requirements

†To ensure the outputs activate in the 3−state condition, the output enable pins

determined by the current sinking capability of the output connected to the OE pin.

http://onsemi.com

MARKING DIAGRAM

A

= Assembly

Location

WL

= Wafer Lot

YY

= Year

WW

= Work Week

TSSOP−48

DT SUFFIX

CASE 1201

1

48

74ALVCH16240DT

AWLYYWW

1

48

Device

Package

Shipping

ORDERING INFORMATION

74ALVCH16240DTR

TSSOP

2500 / Reel