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NCP81042MNTXG Datasheet(PDF) 9 Page - ON Semiconductor |
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NCP81042MNTXG Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 12 page NCP81042 http://onsemi.com 9 L DCR RS1 RS2 CS CSP CSN/VO Figure 5. Differential Current Sense Network Light Load Operation In the light load condition, NCP81042 will work in a diode emulation mode with bottom gate turning off if the inductor current is below zero. The system therefore works in discontinuous conduction mode (DCM). The zero current detection is done by sensing switch node and automatically adjusted to minimize the low side FET body diode conduction time (right after LG turns off) in diode emulation mode. If the load reduces further, COMP signal will be close or below the internal ramp bottom triggering minimum on time operation, the system will start skipping pulses, working in a reduced frequency range. NCP81042 has an internal ultrasonic timer to keep the device from working in an audio frequency and below. This timer initiates after high side gate off signal and expires after ~30 ms. Normally high side gate signal will reset this ultrasonic timer repeatedly before it expires. In a very light load or load release, if there is no high side gate pulses until the timer expires, the low side MOSFET(s) will be forced to turn on to discharge the output. Through properly compensated network the comp signal will climb up to generate next burst of switching pulses and the converter will regulate the output voltage to its target level. This can last a few cycles or continuously depending on the system load level. In light load operation, if synchronization is enabled, NCP81042 will also check the SYNC pin input signal cycle by cycle. If the external sync signal is within the synchronization frequency range, the NCP81042 will interleave its switching pulses with it after a proper delay. In this way, the ripple variation during transition between the discontinuous and continuous current mode can be minimized. Voltage Feedback The NCP81042 allow the output voltage to be adjusted from 0.8 V to 5 V via an external resistor divider network (R1, R2). The controller will regulate the output voltage to maintain the FB pin voltage to 0.8 V reference voltage. The relation between the resistor divider network and the output voltage is as below; R2 + R1 @ 0.8 V Vout * 0.8 V VOUT VFB R1 R2 Figure 6. Feedback Voltage |
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