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SP5502 Datasheet(PDF) 2 Page - Mitel Networks Corporation |
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SP5502 Datasheet(HTML) 2 Page - Mitel Networks Corporation |
2 / 8 page 2 SP5502 ELECTRICAL CHARACTERISTICS TAMB = 10°C to 80°C, VCC = 4·5V to 5·5V. All pin references are to the SP5502S (MP16 package). These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Supply current Prescaler input voltage Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current SDA Output voltage Charge pump current low Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports Sink current Leakage current Input Port P3 input current high P3 input current low Typ. Value Conditions Characteristic Pin 12 13,14 13,14 4,5 4,5 4,5 4,5 4,5 4 1 1 1 16 2 6,7,9-11 6,7,9-11 8 8 12·5 30 3 0 500 10 750 20 48 50 2 50 170 6400 40 60 300 300 VCC 1·5 10 10 10 0·4 5 200 10 1 0·5 Units Min. Max. mA mVrms mVrms Ω pF V V µA µA µA V µA µA nA Ω mV p-p Ω mA µA mA mA VCC = 5V 80MHz to 1GHz 1·3GHz, see Fig. 5 Input voltage = VCC Input voltage = 0V When VCC = 0V Sink current = 3mA Byte 4, bit 2 = 0, pin 1 = 2V Byte 4, bit 2 = 1, pin 1 = 2V Byte 4, bit 4 = 1, pin 1 = 2V V pin 16 = 0·7V Parallel resonant crystal (note 2) VOUT = 0·7V (see note 1) VOUT = 13·2V V pin 8 = VCC V pin 8 = 0V NOTES 1. Source impedance between all output ports and ground is approximately 5 Ω. This should be taken into account when calculating output port saturation voltages. 2. The maximum resistance quoted refers to all conditions, including start-up. FUNCTIONAL DESCRIPTION (Except where otherwise indicated, ‘SP5502’ refers to both variants) The SP5502 is programmed from an I2C BUS. Data and Clock are fed in on the SDA and SCL lines respectively as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C Bus system. Table 3 shows how the address is selected by applying a voltage to P3. The address input is shown in Fig. 6. The LSB of the address Byte (R/W) sets the device into read mode if it is high and write mode if it is low. When the SP5502 receives a correct address Byte it pulls the SDA line low during the acknowledge period and during following acknowl- edge periods after further data Bytes are programmed. When the SP5502 is programmed into the read mode the controlling device accepting the data must pull down the SDA line during the following acknowledge period to read another status Byte. WRITE MODE (FREQUENCY SYNTHESIS) When the device is in the write mode Bytes 2 3 select the synthesised frequency while Bytes 4 5 select the output port states and charge pump information. Once the correct address is received and acknowledged, the first Bit of the next Byte determines whether that Byte is interpreted as Byte 2 or 4, a logic 0 for frequency information and a logic 1 for charge pump and output port information. Additional data Bytes can be entered without the need to re- address the device until an I2C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or AFC purposes. If the transmission of data is stopped mid-byte (i.e., by another device on the bus) then the previously programmed byte is maintained. Frequency data from Bytes 2 and 3 is stored in a 15-bit shift register and is used to control the division ratio of the 15-bit programmable divider which is preceded by a divide-by-8 prescaler and amplifier to give excellent sensitivity at the local oscillator input; see Fig 5. The input impedance is shown in Fig 7. |
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