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SP5658KG Datasheet(PDF) 5 Page - Mitel Networks Corporation |
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SP5658KG Datasheet(HTML) 5 Page - Mitel Networks Corporation |
5 / 14 page 5 SP5658 The output of the preamplifier is fed to the 2/1 selectable prescaler and then to the 17 bit fully programmable divider, which is of MN+A architecture. The M counter is 13 bit and the A counter 4. If bit DE is set to a 0 the prescaler is disabled; Note that the control function DE cannot be used dynamically. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 8 ratios as described in Table 1. The output of the phase comparator feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump can be disabled to a high impedance state by the DISABLE input. The varactor drive output can also be disabled by the OS bit within the data word, so switching the external transistor ‘OFF’ and allowing an external voltage to be written to the varactor line for tuner alignment purposes. The phase comparator also drives the lock detect circuit which generates a lock flag. ‘In–lock’ is indicated by a high impedance state on the lock output. The programmable divider output divided by 2, F pd /2 and the comparison frequency, F comp can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Table 2. ABSOLUTE MAXIMUM RATINGS All voltages are referred to V EE at 0V Characteristics Pin Min Max Units Conditions (SP5658S) Supply voltage, V CC 12 –0.3 7 V RF input voltage 13, 14 2.5 V p–p AC coupled as per application RF input DC offset 13, 14 –0.3 V CC +0.3 V Port voltage 7 – 10 –0.3 14 V Port in off state 7 – 10 –0.3 6 V Port in on state Total port current 7 – 10 50 mA Lock output DC offset 11 –0.3 V CC +0.3 V Charge pump DC offset 1 –0.3 V CC +0.3 V Drive DC offset 16 –0.3 V CC +0.3 V Crystal DC offset 2 –0.3 V CC +0.3 V Data, Clock, Enable & Disable DC 3 – 6 –0.3 V CC +0.3 V offset Storage temperature –55 +125 °C Junction temperature 150 °C MP14 Thermal Resistance Chip to ambient 123 °C/W Chip to case 45 °C/W MP16 Thermal Resistance Chip to ambient 111 °C/W Chip to case 41 °C/W Power consumption at V CC =5.5V 407 mW All ports off, prescaler enabled ESD protection ALL 2 kV MIL–STD 883 TM 3015 FUNCTIONAL DESCRIPTION The SP5658 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The RF preamplifier contains a selectable divide by two for operation above 2.0GHz. Up to 2GHz the RF input interfaces directly with the programmable divider, so eliminating degradation in phase noise due to the prescaler action. The block diagram is shown in Fig.2. The SP5658 is controlled by a standard 3–wire bus comprising data, clock and enable inputs. The programming word for the 16 pin variant contains 28 bits, four of which are used for port selection, 18 to set the programmable divider ratio and enable/disable the prescaler, bit DE, three bits to select the reference division ratio, bits R0–R2, one bit to set charge pump current, bit C0, and the remaining two bits to access test modes, bit T0, and to disable the varactor drive, bit OS. The data word for 14 pin variant is identical to 16 pin except 26 bits only are required, two of which are used for port selection. The programming format is shown in Fig. 3. The clock input is disabled by an enable low signal, data is therefore only clocked into the internal shift registers during an enable high and is loaded into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. |
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