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SP8858IGHPAS Datasheet(PDF) 10 Page - Mitel Networks Corporation |
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SP8858IGHPAS Datasheet(HTML) 10 Page - Mitel Networks Corporation |
10 / 17 page 10 SP8858 signal at the phase detector input. The multiplied reference signal phase noise can set the limit on the achievable close- in phase noise. It is important then that the reference signal is a low phase noise source with good long term stability. The residual noise of the reference divider is also important because, at some offsets from the carrier, the dividers limit the phase noise reduction that is achievable when the reference signal is divided down to FREF. More detailed advice on phase noise optimisation is given in Ref. 1. Charge Pump Output CP OUTPUT (pin 26) and CP REF (pin 5) are connected directly to the inverting and non-inverting input of the loop filter amplifier respectively as shown in Fig. 12. The CP OUTPUT pin will source/sink a current to/from the inverting input equal in magnitude to, or a multiple of, a current reference flowing into RPD (pin 24). The multiplication factor is programmed by two bits (G1 and G2) in the F1 or F2 word (see Data Entry and Control section). The CP OUTPUT has two stable states. The ON state sourcing or sinking a fixed current and an OFF state in which no current will flow from or into the CP output pin. The proportion of time the charge pump is ON depends on the frequency/phase relationship between the reference signal (divided by R) and the VCO signal (divided by N) at the phase detector input: q The digital phase detector is sensitive to a frequency difference between the two input signals and will source or sink a constant current for frequency differences. q When phase-lock is acquired the charge pump current ON/ OFF ratio is in direct proportion to the phase difference between the two signals at the phase detector input. Starting from the state ‘charge pump OFF’ the edge of the leading signal triggers the charge pump into the ON state. The edge of the lagging signal briefly triggers a current at the output which is opposite in sign and equal in magnitude to the current already present before the charge pump returns to the OFF state. When the phase difference reaches zero the input signals simultaneously trigger brief source and sink current pulses which cancel at the output so that zero phase error gives zero output and the deadband is eliminated. The pulse widths are determined by the time taken to reset the internal flip-flops. In practice, when the loop is phase locked and the charge pump is predominately in the OFF state there are two imperfections to consider: q The loop filter capacitors discharge during the period of the reference signal. q A small current leaks into CP OUTPUT in the OFF state at high charge-pump current settings. A small correction is therefore required each cycle. The resulting disturbance is attenuated by the loop but any residual ripple on the VCO control frequency modulates the VCO causing the characteristic reference sidebands. The magnitude of the sidebands that can be tolerated depends entirely on the application and can be reduced by setting a loop bandwidth very much less than the phase detector comparison frequency (FREF) or by reducing the charge-pump current (the leakage current is negligible for low charge-pump currents). The charge-pump can be set to source or sink a current for any given phase difference and the SENSE bit in the F1 (or F2) programme word is used to set the appropriate sign for the application. The SENSE bit should be set to 1 for a VCO with a positive frequency versus control voltage characteristic to ensure phase lock. The actual bias voltage at the CP REF pin varies with the magnitude of the reference current and CP OUT is held at the same voltage by the operational amplifier. A low offset voltage amplifier should be chosen to maintain the match between the reference current into RPD (pin 24) and the actual output current. The simplest method of setting the reference current is to connect a resistor between RPD and the supply. The voltage at pin 24 is approximately 1·5V but this varies slightly with the magnitude of the current and a simple calculation of Ipin 24 = (VCC21·5)/RPD (see Description, Data Entry and Control) is approximate. The voltage at pin 24 will also vary with temperature and the impact of the phase detector gain variations on performance should be assessed in each individual application. If it is considered important to improve the accuracy of the phase detector gain then the use of a constant current source may be more appropriate. Miscellaneous I/Os The SP8858 includes simple lock-detect circuit. The output signals from the Reference and RF dividers are used to drive an EXOR type phase detector. The output of this type of detector is logic high if the inputs are at the same voltage level and low if the inputs are polarised. The EXOR gate drives a buffer stage with the output collector loaded with a single 50k Ω on-chip resistor and a capacitor connected externally at pin 28 (CD). The RC serves to integrate the output pulse train from the phase detector. The capacitor voltage must reach a fixed threshold to enable a constant current sink into pin 27. The inputs POWER DOWN and F1/F2 can either be fixed at the required logic level or controlled by some peripheral circuit. See Table 1 and Fig. 12. As with any RF design work care must be taken with the power supply layout to and the returns from the IC and the physical position of the PLL on the PCB in relation to potential interference sources. The VCC supply inputs should be connected to a well regulated 5V power supply and locally decoupled; noise on the supply can influence the noise power spectrum of the output signal. The programming inputs DATA, CLOCK and ENABLE are compatible with standard CMOS and TTL logic and are subject to the timing restrictions shown in Fig. 4. Loop Filter Design The linear model of the PLL, as shown in Fig.7, includes an external loop-filter F(s). A filter is required that will: q Add a zero to the open-loop transfer function thus allowing the designer to manipulate the closed-loop root locations through the appropriate choice of filter components. Without the filter (F(s) = 1) the closed loop is first order with the root locus travelling along the negative real axis with increasing DC gain. In this situation the designer has very little control over the fo(s)/fi(s) transfer characteristic because the selection of the gain factor KPD KVCO/N may, in practice, be limited. q Introduce a second pole at the origin in order to increase the type number of the loop to type II. This is required to ensure that the steady state error signal tends to zero for a ramp in phase. In addition, a suitable interface is required to provide the transimpedance function from the charge-pump output to the VCO thus converting the output signal, in the form of current pulses, to the voltage signal required at the VCO input. The required transfer function is therefore F(s) = (s+a)/s (zero at 2a) and the loop filter is implemented using the circuit and formula shown in Fig. 10a. The closed-loop transfer function becomes: fo(s)/fi(s) = (st111)KVCOKPD/(s21st1K/C11K/C1) where K = KVCOKPD/N t1 = C1R1 |
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