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SM5902AF Datasheet(PDF) 8 Page - Nippon Precision Circuits Inc |
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SM5902AF Datasheet(HTML) 8 Page - Nippon Precision Circuits Inc |
8 / 40 page NIPPON PRECISION CIRCUITS-8 SM5902AF Parameter Symbol Condition Rating Unit Min Typ Max ZSCK pulsewidth tSCOW 15 pF load 1/96fs ZSCK pulse cycle tSCOY 15 pF load 1/48fs ZSRDATA and ZLRCK output delay time tDHL 15 pF load 0 60 ns tDLH 15 pF load 0 60 ns DRAM access timing (NRAS, NCAS, NCAS2, NWE, A0 to A10, D0 to D3) Parameter Symbol Condition Rating Unit Min Typ Max NRAS pulsewidth tRASL 15 pF load 5 tCY(note) tRASH 15 pF load 3 tCY NRAS falling edge to NCAS falling edge tRCD 15 pF load 2 tCY NCAS pulsewidth tCASH 15 pF load 5 tCY tCASL 15 pF load 3 tCY NRAS Setup time tRADS 15 pF load 1 tCY falling edge to address Hold time tRADH 15 pF load 1 tCY NCAS Setup time tCADS 15 pF load 1 tCY falling edge to address Hold time tCADH 15 pF load 5 tCY NCAS Setup time tCWDS 15 pF load 3 tCY falling edge to data write Hold time tCWDH 15 pF load 3 tCY NCAS Input setup tCRDS 40 ns rising edge to data read Input hold tCRDH 0ns NWE pulsewidth tWEL 15 pF load 6 tCY NWE falling edge to NCAS falling edge tWCS 15 pF load 3 tCY Non compression 1.5 ms Refresh cycle 1M 6-bit compression 3.7 ms (fs = 44.1 kHz playback) DRAM 5-bit compression 4.4 ms tREF × 1 4-bit compression 5.5 ms Memory system ON Non compression 3.0 ms Decode sequence operation 4M 6-bit compression 7.3 ms (RDEN=H) DRAM 5-bit compression 8.8 ms × 1 or × 2 4-bit compression 10.9 ms Non compression 5.9 ms 16M 6-bit compression 14.6 ms DRAM 5-bit compression 17.5 ms × 1 4-bit compression 21.8 ms Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz ZSCK ZSRDATA 0.5VDD DLH ZLRCK 0.5VDD DHL ttDLH SCOW t tSCOW t SCOY t Serial output (ZSRDATA, ZLRCK, ZSCK pins) |
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