LM95241

SNIS143E – AUGUST 2006 – REVISED MARCH 2013

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Logic Electrical Characteristics Digital DC Characteristics

Symbol

Parameter

Conditions

Units

(Limit)

SMBDAT, SMBCLK INPUTS

Logical “1” Input Voltage

2.1

V (min)

Logical “0”Input Voltage

0.8

V (max)

SMBDAT and SMBCLK Digital Input

400

mV

Hysteresis

Logical “1” Input Current

0.005

±10

µA (max)

Logical “0” Input Current

−0.005

±10

µA (max)

Input Capacitance

5

pF

SMBDAT OUTPUT

High Level Output Current

10

µA (max)

SMBus Low Level Output Voltage

0.4

V (max)

0.6

(1)

specifications are not ensured.

(2)

Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

Logic Electrical Characteristics SMBus Digital Switching Characteristics

The switching characteristics of the LM95241 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95241. They

adhere to but are not necessarily the SMBus bus specifications.

Symbol

Parameter

Conditions

Units

(Limit)

SMBus Clock Frequency

100

kHz (max)

10

kHz (min)

SMBus Clock Low Time

4.7

µs (min)

25

ms (max)

SMBus Clock High Time

4.0

µs (min)

SMBus Rise Time

1

µs (max)

SMBus Fall Time

0.3

µs (max)

Output Fall Time

250

ns (max)

(4)

SMBDAT and SMBCLK Time Low for Reset of

25

ms (min)

35

ms (max)

Data In Setup Time to SMBCLK High

250

ns (min)

Data Out Stable after SMBCLK Low

300

ns (min)

1075

ns (max)

Start Condition SMBDAT Low to SMBCLK Low

100

ns (min)

(Start condition hold before the first clock falling

edge)

Stop Condition SMBCLK High to SMBDAT Low

100

ns (min)

(Stop Condition Setup)

SMBus Repeated Start-Condition Setup Time,

0.6

µs (min)

SMBCLK High to SMBDAT Low

(1)

specifications are not ensured.

(2)

Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

(3)

(4)

(5)

therefore setting SMBDAT and SMBCLK pins to a high impedance state.

6

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